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Intel 82543GC, Обновление спецификации

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82543GC Gigabit Ethernet Controller Specification Update 

10                                                                        

 

26 

X 

X 

X 

NoFix 

Default Speed Selection May Depend on EEPROM Presence 

15  

27 

X 

X 

X 

NoFix 

Link Status Change Interrupt Only Occurs If Link is Up 

15  

28 

X 

X 

X 

NoFix 

Early Transmit Feature Does Not Operate Correctly 

15  

29 

X 

X 

X 

NoFix 

TDO Output Not Floated When JTAG TAP Controller Inactive 

16  

30 

X 

X 

X 

NoFix 

Initialization Ignores Incorrect EEPROM Signature 

16  

31 

X 

X 

X 

NoFix 

Internal Loopback Difficulties 

16  

32 

X 

X 

X 

NoFix 

Collision Pin Not Ignored in TBI Mode 

16  

33 

X 

X 

X 

NoFix 

Receive Descriptor Writeback Problems for Packets Spanning 
Multiple Buffers 

17  

34 

X 

X 

X 

NoFix 

Illegal Oversize Packets Overflow Receive FIFO 

17  

35 

X 

X 

X 

NoFix 

Transmit Descriptor Writeback Problem with Non-Zero 
WTHRESH 

17  

36 

X 

X 

X 

NoFix 

Bus Initialization with Some Chipsets 

17  

37 

X 

X 

X 

NoFix 

Use of Receive Delay Timer Ring Register (RDTR) Causes 
Occasional Lockups 

18  

38 

X 

X 

X 

NoFix 

Transmit TCP Checksum Modified if Calculated as 0x0000 

18  

 

 

 

 

 

 

 

 

No. 

A0 

A1 

A2

 

Plans 

SPECIFICATION CLARIFICATIONS 

Page 

Affected 

Document 

1 

X 

X 

X 

Doc 

Change 

0-70C Ambient Temperature Range 

19 

Datasheet  

2 

X 

X 

X 

Doc 

Change 

Receiver Enabling and Disabling 

19 

Developer’s 
Manual 

 

 

 

 

 

 

 

 

No. 

A0 

A1 

A2

 

Plans 

DOCUMENTATION CHANGES 

Page 

Affected 

Document 

1 

X 

X 

X 

Doc 

Replaced 

TX/RX Descriptor Register Addresses 

19 

Developer’s 
Manual    

2 

X 

X 

X 

Doc 

Replaced 

Auto Speed Detect Function Requires CTRL.SLU Bit  to Be Set 

20 

Developer’s 
Manual    

3 

X 

X 

X 

Doc 

Replaced 

Values Programmed to Some Registers While in Reset Do Not 
Persist 

20 

Developer’s 
Manual    

4 

X 

X 

X 

Doc 

Change 

JTAG Port Operation 

20 

Datasheet and  
Developer’s 
Manual. 

5 

X 

X 

X 

Doc 

Change 

Register Summary Uses Improper Page Reference Format 

20 

Developer’s 
Manual  

6 

X 

X 

X 

Doc 

Change 

Change O_EN_CDET output to NO_CONNECT 

21 

Datasheet  

7 

X 

X 

X 

Doc 

Change 

Change Recommended Tx IPG Programming Value for 
10/100/1000BASE-T 

21 

Developer’s 
Manual  

8 

X 

X 

X 

Doc 

Change 

Remove Transmit Report Status Sent Function 

21 

Developer’s 
Manual 

9 

X 

X 

X 

Doc 

Change 

Remove Transmit  DMA Pre-fetching and Preemption 
Functions (TXDMAC) 

21 

Developer’s 
Manual  

10 

X 

X 

X 

Doc 

Change 

Remove Transmit Burst Timer Control Function (TBT) 

22 

Developer’s 
Manual 

11 

X 

X 

X 

Doc 

Change 

Remove Adaptive IFS Throttle Function (AIT)  

22 

Developer’s 
Manual 

 

Содержание 82543GC

Страница 1: ...June 18 2004 Revision 2 1 The 82543GC Gigabit Ethernet Controller may contain design defects or errors known as errata that may cause the product to deviate from published specifications Current chara...

Страница 2: ...t descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definit...

Страница 3: ...and 100Mb Operation 13 9 CRS Detection Takes Too Long in MII Half Duplex Mode 13 10 DMA Early Receive Function Does Not Work 13 11 ILOS Bit Copied Incorrectly from EEPROM to Speed Bits 13 12 Gigabit...

Страница 4: ...gister RDTR Causes Occasional Lockups 20 38 Transmit TCP Checksum Incorrectly Modified if Calculated as 0x0000 20 SPECIFICATION CLARIFICATIONS 21 1 0 70C Ambient Temperature Range 21 2 Receiver Enabli...

Страница 5: ...GC Gigabit Ethernet Controller Specification Update 5 REVISION HISTORY 82543GC Gigabit Ethernet Controller Specification Update Date of Revision Revision Description June 18 2004 2 1 Initial Public Re...

Страница 6: ...82543GC Gigabit Ethernet Controller Specification Update 6 Note This page is intentionally left blank...

Страница 7: ...es will be incorporated in the next release of the specifications Errata are design defects or errors Errata may cause 82543GC device behavior to deviate from published specifications Hardware and sof...

Страница 8: ...ed with either QDF number or S spec number A2 Q417 N A FW82543GC or TL82543GC Engineering Samples May be marked two ways with the QDF number and a top mark FW82543GC or without any QDF or S spec numbe...

Страница 9: ...Maximum Size Limitation 9 3 X Fixed Late Collision Statistics May Be Incorrect 9 4 X Fixed Some Registers Cannot be Accessed During Reset 10 5 X X X NoFix DAC Accesses May Not Be Interpreted Correctly...

Страница 10: ...Page Affected Document 1 X X X Doc Change 0 70C Ambient Temperature Range 19 Datasheet 2 X X X Doc Change Receiver Enabling and Disabling 19 Developer s Manual No A0 A1 A2 Plans DOCUMENTATION CHANGES...

Страница 11: ...out data transfer In response the 82543GC controller may attempt another read or write cycle to a different address instead of retrying the same memory location In a PC environment it is possible that...

Страница 12: ...karound Bit 0x0D in the EEPROM space at byte 0x0A denotes 64 bit address mapping if cleared to 0 This is the default configuration Program the bit to logic 1 to denote 32 bit address space As an added...

Страница 13: ...ated in operating networks however Workaround None Status Intel resolved this erratum in the A1 stepping of the 82543GC Gigabit Ethernet Controller 10 DMA Early Receive Function Does Not Work Problem...

Страница 14: ...tion Do not use the TCP segmentation feature Workaround None Status Some of the errata were corrected in the A1 stepping At least one severe transmit problem was not corrected Intel does not plan to r...

Страница 15: ...er 19 Transmit Packet Corruption of Small Packets Problem When the 82543GC Ethernet Controller is transmitting and receiving simultaneously it is possible that short packets will be corrupted before t...

Страница 16: ...e problem may not be seen with some link partners particular those that are not in strict IEEE compliance with respect to collisions Implication The 82543GC Gigabit Ethernet Controller cannot be used...

Страница 17: ...efault speed setting CTRL SPEED will depend on whether a valid EEPROM is present as determined by the signature bits If a legitimate EEPROM is determined not to be present the controller will use 10b...

Страница 18: ...tects any other value it Is supposed to abort processing initialization data and use its defaults instead With this erratum the controller continues processing the EEPROM initialization values even if...

Страница 19: ...he following precautions Configure the receive interrupt to occur immediately on end of packet by programming RDTR 0 Configure the descriptor writeback threshold WTHRESH to a value that will not resul...

Страница 20: ...ter RDTR is used to delay interrupt notification until a number of microseconds elapse past the last receive packet in a sequence of packets Under high traffic conditions this function can occasionall...

Страница 21: ...eiver by programming the Enable EN Bit in the Receive Control Register RCTL The reason is that the disabling enabling operation does not re initialize packet filter logic that demarcates packet start...

Страница 22: ...et developer s manual documents indicated in the preface of this spec update 3 Values Programmed to Some Registers While in Reset Do Not Persist Problem This behavior is related to erratum 4 Some Regi...

Страница 23: ...Register The actual inter packet gap in MAC data clocks is the sum of the programmed value and a variable logic synchronization time within the device Use a recommended programming value of 10 for TB...

Страница 24: ...Transmit Burst Timer Register TBT will be removed from the developer s manual Note Erratum 12 prohibits Gigabit half duplex mode operation Affected Docs OR 2710 82543GC Gigabit Ethernet Controller De...

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