Intel 82543GC Скачать руководство пользователя страница 13

82543GC Gigabit Ethernet Controller Specification Update 

 

 

 

 

13

Implication

:  

Data transfer performance is substantially reduced due to error packets. 

Workaround

:  

None.   

Status:

  

Intel resolved this erratum in the A1 stepping of the 82543GC Gigabit Ethernet Controller. 

8.  48 Bit Preambles Sent in 10Mb and 100Mb Operation 

 

Problem:   

The 82543GC device transmits 48 bit preambles instead of 56 bit preambles for 10Mb and 100Mb operation. 

Implication:  

Certain 10Mb and 100Mb repeaters will only tolerate 56 bit preambles, so packets transmitted by the 82543GC 
controller will be incompatible. A product example is the Intel InBusiness 4 Port Fast Hub, which is based on a 
Broadcom 5205 repeater device. 

Workaround: 

 None. 

Status:

  

Intel resolved this erratum in the A1 stepping of the 82543GC Gigabit Ethernet Controller. 

9.  CRS Detection Takes Too Long in MII Half-Duplex Mode 

 

Problem

:  

When the 82543GC controller is operated in half-duplex mode, it can take up to 16 bit times to detect Carrier 
Sense (CRS) assertion. 

Implication:  

The IEEE specification is 8 bit times. Functional problems are not anticipated in operating networks, however. 

Workaround: 

 None. 

Status:

  

Intel resolved this erratum in the A1 stepping of the 82543GC Gigabit Ethernet Controller. 

10. DMA Early Receive Function Does Not Work 

 

Problem:   

When DMA early receive operation is enabled on the 82543GC device and a DMA receive underrun occurs, the 
controller may erroneously place data into the packet descriptors. 

Implication:  

The early receive function cannot be used. 

Workaround: 

 None. 

Status:

  

Intel does not plan to resolve this erratum in a future stepping of the 82543GC Gigabit Ethernet Controller. 

11. ILOS Bit Copied Incorrectly from EEPROM to Speed Bits 

 

Problem

:  

When the 82543GC controller loads configuration information from EEPROM, it maps the Invert Loss of Signal 
(ILOS) bit into the Speed Selection bits in the device control register.  

Implication

:  

Both the ILOS and Speed settings will be incorrect. 

Workaround

:  

Software should write correct bit values into the control register. 

Status:

  

Intel resolved this erratum in the A1 stepping of the 82543GC Gigabit Ethernet Controller. 

12. Gigabit Half-Duplex Mode Operates Incorrectly 

 

Problem

:  

Several problems prevent proper gigabit half-duplex operation. 

Implication

:  

Do not use GMII half-duplex operation. GMII full-duplex and MII (10/100Mb) half-duplex modes are unaffected. 

Содержание 82543GC

Страница 1: ...June 18 2004 Revision 2 1 The 82543GC Gigabit Ethernet Controller may contain design defects or errors known as errata that may cause the product to deviate from published specifications Current chara...

Страница 2: ...t descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definit...

Страница 3: ...and 100Mb Operation 13 9 CRS Detection Takes Too Long in MII Half Duplex Mode 13 10 DMA Early Receive Function Does Not Work 13 11 ILOS Bit Copied Incorrectly from EEPROM to Speed Bits 13 12 Gigabit...

Страница 4: ...gister RDTR Causes Occasional Lockups 20 38 Transmit TCP Checksum Incorrectly Modified if Calculated as 0x0000 20 SPECIFICATION CLARIFICATIONS 21 1 0 70C Ambient Temperature Range 21 2 Receiver Enabli...

Страница 5: ...GC Gigabit Ethernet Controller Specification Update 5 REVISION HISTORY 82543GC Gigabit Ethernet Controller Specification Update Date of Revision Revision Description June 18 2004 2 1 Initial Public Re...

Страница 6: ...82543GC Gigabit Ethernet Controller Specification Update 6 Note This page is intentionally left blank...

Страница 7: ...es will be incorporated in the next release of the specifications Errata are design defects or errors Errata may cause 82543GC device behavior to deviate from published specifications Hardware and sof...

Страница 8: ...ed with either QDF number or S spec number A2 Q417 N A FW82543GC or TL82543GC Engineering Samples May be marked two ways with the QDF number and a top mark FW82543GC or without any QDF or S spec numbe...

Страница 9: ...Maximum Size Limitation 9 3 X Fixed Late Collision Statistics May Be Incorrect 9 4 X Fixed Some Registers Cannot be Accessed During Reset 10 5 X X X NoFix DAC Accesses May Not Be Interpreted Correctly...

Страница 10: ...Page Affected Document 1 X X X Doc Change 0 70C Ambient Temperature Range 19 Datasheet 2 X X X Doc Change Receiver Enabling and Disabling 19 Developer s Manual No A0 A1 A2 Plans DOCUMENTATION CHANGES...

Страница 11: ...out data transfer In response the 82543GC controller may attempt another read or write cycle to a different address instead of retrying the same memory location In a PC environment it is possible that...

Страница 12: ...karound Bit 0x0D in the EEPROM space at byte 0x0A denotes 64 bit address mapping if cleared to 0 This is the default configuration Program the bit to logic 1 to denote 32 bit address space As an added...

Страница 13: ...ated in operating networks however Workaround None Status Intel resolved this erratum in the A1 stepping of the 82543GC Gigabit Ethernet Controller 10 DMA Early Receive Function Does Not Work Problem...

Страница 14: ...tion Do not use the TCP segmentation feature Workaround None Status Some of the errata were corrected in the A1 stepping At least one severe transmit problem was not corrected Intel does not plan to r...

Страница 15: ...er 19 Transmit Packet Corruption of Small Packets Problem When the 82543GC Ethernet Controller is transmitting and receiving simultaneously it is possible that short packets will be corrupted before t...

Страница 16: ...e problem may not be seen with some link partners particular those that are not in strict IEEE compliance with respect to collisions Implication The 82543GC Gigabit Ethernet Controller cannot be used...

Страница 17: ...efault speed setting CTRL SPEED will depend on whether a valid EEPROM is present as determined by the signature bits If a legitimate EEPROM is determined not to be present the controller will use 10b...

Страница 18: ...tects any other value it Is supposed to abort processing initialization data and use its defaults instead With this erratum the controller continues processing the EEPROM initialization values even if...

Страница 19: ...he following precautions Configure the receive interrupt to occur immediately on end of packet by programming RDTR 0 Configure the descriptor writeback threshold WTHRESH to a value that will not resul...

Страница 20: ...ter RDTR is used to delay interrupt notification until a number of microseconds elapse past the last receive packet in a sequence of packets Under high traffic conditions this function can occasionall...

Страница 21: ...eiver by programming the Enable EN Bit in the Receive Control Register RCTL The reason is that the disabling enabling operation does not re initialize packet filter logic that demarcates packet start...

Страница 22: ...et developer s manual documents indicated in the preface of this spec update 3 Values Programmed to Some Registers While in Reset Do Not Persist Problem This behavior is related to erratum 4 Some Regi...

Страница 23: ...Register The actual inter packet gap in MAC data clocks is the sum of the programmed value and a variable logic synchronization time within the device Use a recommended programming value of 10 for TB...

Страница 24: ...Transmit Burst Timer Register TBT will be removed from the developer s manual Note Erratum 12 prohibits Gigabit half duplex mode operation Affected Docs OR 2710 82543GC Gigabit Ethernet Controller De...

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