Intel 80331, Руководство по конструкции

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Intel® 80331 I/O Processor Design Guide
Memory Controller
Memory Controller
7
The Memory Controller allows direct control of a DDR SDRAM memory subsystem. It features
programmable chip selects and support for error correction codes (ECC). The memory controller can
be configured for DDR SDRAM at 333 MHz and DDR-II at 400MHz. The memory controller
supports pipelined access and arbitration control to maximize performance. The memory controller
interface configuration support includes Unbuffered DIMMs, Registered DIMMs, and discrete DDR
SDRAM devices.
External memory can be configured as host addressable memory or private 80331memory utilizing
the Address Translation Unit and Bridge.
7.1 DDR Bias Voltages
The 80331 supports 2.5 V DDR memory and 1.8V for DDRII. Table 27 lists the
minimum/maximum values for the DDR memory bias voltages and Table 28 lists the
minimum/maximum values for the DDR II memory bias voltages.
Table 27. DDR Bias Voltages
Symbol Parameter Minimum Maximum Units
V
CC25
2.5 V Power balls to be connected to a 2.5 V power board plane. 2.3 2.7 V
V
DDQ
I/O Supply Voltage 2.3 2.7 V
V
REF
Memory I/O Reference Voltage V
CC25
/2 - 0.05 V
CC25
/2 + 0.05 V
V
TT
DDR Memory I/O Termination Voltage V
REF
- 0.04 V
REF
+ 0.04 V
Table 28. DDR II Bias Voltage
Symbol Parameter Minimum Maximum Units
V
CC18
1.8 V Power balls to be connected to the 1.8 V power board plane. 1.7 1.9 V
V
DDQ
I/O Supply Voltage 1.7 1.9 V
V
REF
Memory I/O Reference Voltage V
CC/18
/2 - 0.05 V
CC/18
/2 + 0.05 V
V
TT
DDR Memory I/O Termination Voltage V
REF
- 0.04 V
REF
+ 0.04 V