8
Specification Update
Summary Tables of Changes
The following tables indicate the errata, specification changes, specification
clarifications, or documentation changes which apply to the processor. Intel may fix
some of the errata in a future stepping of the component, and account for the other
outstanding issues through documentation or specification changes as noted. These
tables uses the following notations:
Codes Used in Summary Tables
Stepping
X:
Errata exists in the stepping indicated. Specification Change or
Clarification that applies to this stepping.
(No mark)
or (Blank box):
This erratum is fixed in listed stepping or specification change
does not apply to listed stepping.
Page
(Page):
Page location of item in this document.
Status
Doc:
Document change or update will be implemented.
Plan Fix:
This erratum may be fixed in a future stepping of the product.
Fixed:
This erratum has been previously fixed.
No Fix:
There are no plans to fix this erratum.
Row
Change bar to left of a table row indicates this erratum is either new or modified from
the previous version of the document.
Errata (Sheet 1 of 4)
Number
Steppings
Status
ERRATA
D-2
Q-0
BJ1
X
X
No Fix
BJ2
X
X
No Fix
APIC Error “Received Illegal Vector” May be Lost
BJ3
X
X
No Fix
An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May also Result in a
System Hang
BJ4
X
X
No Fix
B0-B3 Bits in DR6 For Non-Enabled Breakpoints May be Incorrectly Set
BJ5
X
X
No Fix
Changing the Memory Type for an In-Use Page Translation May Lead to Memory-
Ordering Violations
