38
Specification Update
BJ76.
A Read from The APIC-Timer CCR May Disarm The TSC_Deadline
Counter
Problem:
When in TSC Deadline mode with TSC_Deadline timer armed
(IA32_TSC_DEADLINE<>0, MSR 6E0H), a read from the local APIC’s CCR (current
count register) using RDMSR 0839H may disarm the TSC Deadline timer without
generating an interrupt as specified in the APIC Timer LVT (Local Vector Table) entry.
Implication:
Due to this erratum, unexpected disarming of the TSC_Deadline counter and possible
loss of an interrupt may occur.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ77.
An Unexpected PMI May Occur After Writing a Large Value to
IA32_FIXED_CTR2
Problem:
If the fixed-function performance counter IA32_FIXED_CTR2 MSR (30BH) is configured
to generate a performance-monitor interrupt (PMI) on overflow and the counter’s value
is greater than FFFFFFFFFFC0H, then this erratum may incorrectly cause a PMI if
software performs a write to this counter.
Implication:
A PMI may be generated unexpectedly when programming IA32_FIXED_CTR2. Other
than the PMI, the counter programming is not affected by this erratum as the
attempted write operation does succeed.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
