Intel 2ND GENERATION INTEL CORE PROCESSOR FAMILY MOBILE - SPECIFICATION UPDATE 01-2011, Спецификация

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10 Specification Update
BJ34
X X No Fix
Malformed PCIe Transactions May be Treated as Unsupported Requests Instead of
as Critical Errors
BJ35
X X No Fix PCIe Root Port May Not Initiate Link Speed Change
BJ36
X X No Fix
Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR or XSAVE/
XRSTOR Image Leads to Partial Memory Update
BJ37
X X No Fix Performance Monitor SSE Retired Instructions May Return Incorrect Values
BJ38
X X No Fix
FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which
Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in 64-bit Mode
BJ39
X X No Fix
FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which
Wraps a 64-Kbyte Boundary in 16-Bit Code
BJ40
X X No Fix Spurious Interrupts May be Generated From the Intel® VT-d Remap Engine
BJ41
X X No Fix
Fault Not Reported When Setting Reserved Bits of Intel® VT-d Queued Invalidation
Descriptors
BJ42
X X No Fix
VPHMINPOSUW Instruction in Vex Format Does Not Signal #UD When vex.vvvv
!=1111b
BJ43
X X No Fix
LBR, BTM or BTS Records May have Incorrect Branch From Information After an
EIST/T-state/S-state/C1E Transition or Adaptive Thermal Throttling
BJ44
X X No Fix
VMREAD/VMWRITE Instruction May Not Fail When Accessing an Unsupported
Field in VMCS
BJ45
X X No Fix Clock Modulation Duty Cycle Cannot be Programmed to 6.25%
BJ46
X X No Fix
Execution of VAESIMC or VAESKEYGENASSIST With An Illegal Value for
VEX.vvvv May Produce a #NM Exception
BJ47
X X No Fix Memory Aliasing of Code Pages May Cause Unpredictable System Behavior
BJ48
X X No Fix
PCI Express Graphics Receiver Error Reported When Receiver With L0s Enabled
and Link Retrain Performed
BJ49
X X No Fix Unexpected #UD on VZEROALL/VZEROUPPER
BJ50
X X No Fix Perfmon Event LD_BLOCKS.STORE_FORWARD May Overcount
BJ51
X X No Fix
Conflict Between Processor Graphics Internal Message Cycles And Graphics
Reads From Certain Physical Memory Ranges May Cause a System Hang
BJ52
X X No Fix
Execution of Opcode 9BH with the VEX Opcode Extension May Produce a #NM
Exception
BJ53
X X No Fix
Executing The GETSEC Instruction While Throttling May Result in a Processor
Hang
BJ54
X X No Fix
A Write to the IA32_FIXED_CTR1 MSR May Result in Incorrect Value in Certain
Conditions
BJ55
X X No Fix
Instruction Fetch May Cause Machine Check if Page Size and Memory Type Was
Changed Without Invalidation
BJ56
X X No Fix
Reception of Certain Malformed Transactions May Cause PCIe Port to Hang
Rather Than Reporting an Error
BJ57
X X No Fix PCIe LTR Incorrectly Reported as Being Supported
BJ58
X X No Fix
PerfMon Overflow Status Can Not be Cleared After Certain Conditions Have
Occurred
BJ59
X X No Fix
XSAVE Executed During Paging-Structure Modification May Cause Unexpected
Processor Behavior
Errata (Sheet 3 of 4)
Number
Steppings
Status ERRATA
D-2 Q-0