IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -31
Q3651 : ES29LV800ET-70TG (8 Mbit Flash Memory)
BLOCK DIAGRAM
DTR-6.8
Command
Register
Analog Bias
Generator
Add
re
s
s Latch
BYTE#
CE#
OE#
A<0:18>
RESET#
Vcc
Vss
Chip Enable
Output Enable
Logic
Vcc Detector
Timer/
Counter
Y-Decoder
X-Decoder
Y-Decoder
Cell Array
Data Latch/
Sense Amps
Input/Output
Buffers
Sector Switches
DQ0-DQ15(A-1)
RY/BY#
Write
State
Machine
WE
#