IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -29
Q3551 : ES29LV400ET-70TG (4 Mbit Flash Memory)
BLOCK DIAGRAM
DTR-6.8
OE#
Vcc
Vss
X-Decoder
DQ0-DQ15(A-1)
Input/Output
Buffers
Data Latch/
Sense Amps
Y-Decoder
Cell Array
WE#
RY/BY#
Vcc Detector
Timer/
Counter
RESET#
A<0:17>
Sector Switches
Command
Register
Write
State
Machine
CE#
BYTE#
Chip Enable
Output Enable
Logic
Y-Decoder
Address Latch
Analog Bias
Generator