Q2802: IS25C02(2 kbit EEPROM)
BLOCK DIAGRAM
TERMINAL DESCRIPTION
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -82
DTR-6.8
PIN CONFIGURATION
STATUS
REGISTER
256 x 8/512 x 8
MEMORY ARRAY
HOLD
CS
WP
CLOCK
SO
OUTPUT
BUFFER
SCK
SI
DATA
REGISTER
MODE
DECODE
LOGIC
GND
VCC
ADDRESS
DECODER
1
2
3
4
8
7
6
5
CS
SO
WP
GND
VCC
HOLD
SCK
SI
CS
Chip Select
SCK
Serial Data Clock
SI
Serial Data Input
SO
Serial Data Output
GND
Ground
V
CC
Power
WP
Write Protect
HOLD
Suspends Serial Input