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TB-FMCH-HDMI2 Hardware User Manual
43
Rev.1.05
Pin Name
No.
IO
Spec.
Description
HA22_N
T22
IO
LVCMOS25
Unused
HA23_N
V22
IO
LVCMOS25
Unused
TX#0_D35
Y18
O
LVCMOS33
TX#0 Video data 35 (FPGA to TX)
TX#0_D34
T16
O
LVCMOS33
TX#0 Video data 34 (FPGA to TX)
TX#0_D33
T15
O
LVCMOS33
TX#0 Video data 33 (FPGA to TX)
TX#0_D32
U17
O
LVCMOS33
TX#0 Video data 32 (FPGA to TX)
TX#0_D31
U16
O
LVCMOS33
TX#0 Video data 31 (FPGA to TX)
TX#0_D30
V19
O
LVCMOS33
TX#0 Video data 30 (FPGA to TX)
TX#0_D29
V18
O
LVCMOS33
TX#0 Video data 29 (FPGA to TX)
TX#0_D28
R16
O
LVCMOS33
TX#0 Video data 28 (FPGA to TX)
TX#0_D27
R15
O
LVCMOS33
TX#0 Video data 27 (FPGA to TX)
TX#0_D26
V17
O
LVCMOS33
TX#0 Video data 26 (FPGA to TX)
TX#0_D25
W17
O
LVCMOS33
TX#0 Video data 25 (FPGA to TX)
TX#0_D24
V15
O
LVCMOS33
TX#0 Video data 24 (FPGA to TX)
TX#0_D23
AA18
O
LVCMOS33
TX#0 Video data 23 (FPGA to TX)
TX#0_D22
AB18
O
LVCMOS33
TX#0 Video data 22 (FPGA to TX)
TX#0_D21
Y17
O
LVCMOS33
TX#0 Video data 21 (FPGA to TX)
TX#0_D20
AB17
O
LVCMOS33
TX#0 Video data 20 (FPGA to TX)
TX#0_D19
AA14
O
LVCMOS33
TX#0 Video data 19 (FPGA to TX)
TX#0_D18
AB14
O
LVCMOS33
TX#0 Video data 18 (FPGA to TX)
TX#0_D17
Y16
O
LVCMOS33
TX#0 Video data 17 (FPGA to TX)
TX#0_D16
W15
O
LVCMOS33
TX#0 Video data 16 (FPGA to TX)
TX#0_D15
V13
O
LVCMOS33
TX#0 Video data 15 (FPGA to TX)
TX#0_D14
W13
O
LVCMOS33
TX#0 Video data 14 (FPGA to TX)
TX#0_D13
AA16
O
LVCMOS33
TX#0 Video data 13 (FPGA to TX)
TX#0_D12
AB16
O
LVCMOS33
TX#0 Video data 12 (FPGA to TX)
TX#0_D11
W14
O
LVCMOS33
TX#0 Video data 11 (FPGA to TX)
TX#0_D10
Y14
O
LVCMOS33
TX#0 Video data 10 (FPGA to TX)
TX#0_D9
Y15
O
LVCMOS33
TX#0 Video data 9 (FPGA to TX)
TX#0_D8
AB15
O
LVCMOS33
TX#0 Video data 8 (FPGA to TX)
TX#0_D7
T12
O
LVCMOS33
TX#0 Video data 7 (FPGA to TX)
TX#0_D6
U12
O
LVCMOS33
TX#0 Video data 6 (FPGA to TX)
TX#0_D5
T14
O
LVCMOS33
TX#0 Video data 5 (FPGA to TX)
TX#0_D4
R13
O
LVCMOS33
TX#0 Video data 4 (FPGA to TX)
TX#0_D3
R11
O
LVCMOS33
TX#0 Video data 3 (FPGA to TX)
TX#0_D2
T11
O
LVCMOS33
TX#0 Video data 2 (FPGA to TX)
TX#0_D1
AA10
O
LVCMOS33
TX#0 Video data 1 (FPGA to TX)
TX#0_D0
AB10
O
LVCMOS33
TX#0 Video data 0 (FPGA to TX)
TX#0_DCLK
W12
O
LVCMOS33
TX#0 DCLK signal (FPGA to TX)
SYSCLK_P
Y11
I
LVCMOS33
System clock (27MHz)
TX#0_DE
W11
O
LVCMOS33
TX#0 data enable (FPGA to TX)
TX#0_HSYNC
Y9
O
LVCMOS33
TX#0 HSYNC (FPGA to TX)