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5.1 Serial Port WRITE Operation
Table 1. Timing Characteristics
Parameter
Conditions
Min
Typ
Max
Units
t
1
SEN to SCK Setup Time
8
nsec
t
2
SDI to SCK Setup Time
10
nsec
t
3
SDI to SCK Hold Time
10
nsec
t
4
SCK High Duration
8
nsec
t
5
SCK Low Duration
8
nsec
t
6
SEN High Duration
640
nsec
A typical WRITE cycle is shown in
a. The Master (host) both asserts SEN (Serial Port Enable) and clears SDI to indicate a WRITE cycle,
followed by a rising edge of SCK.
b. The slave (synthesizer) reads SDI on the 1st rising edge of SCK after SEN. SDI low initiates the
Write cycle (/WR).
c. Host places the six address bits on the next six falling edges of SCK, MSB first.
d. Slave reads the address bits in the next six rising edges of SCK (2-7).
e. Host places the 24 data bits on the next 24 falling edges of SCK, MSB first.
f.
Slave reads the data bits on the next 24 rising edges of SCK (8-31).
g. SEN is de-asserted on the 32nd falling edge of SCK.
h. The 32nd falling edge of SCK completes the cycle.
Figure 5. Serial Port Timing Diagram - Write Serial Port WRITE Operation
5.2 Main Serial Port READ Operation
The synthesizer uses the multi-purpose pin, LD, for both Lock Detect and Serial Data Out (SDO) functions.
The registers lkd_to_sdo_automux_en (
<13>) determine
how the Data Output pin is muxed with the Lock Detect function. If both of the registers are cleared, then
