User Manual | PE11S100X Series Synthesizer
26
7.24 Reg 16h CW Sweep Ramp Step Number Register
Bit
Type
Name
Default
Description
23:0
R/W
ramp_steps_number
2048
Ramp Number of steps in ramp
7.25 Reg 17h CW Sweep Dwell Time Register
Bit
Type
Name
Default
Description
23:0
R/W
ramp_dwell_time
2048
Ramp Number of cycles to hold at top/bottom in
repeat mode
7.26 Reg 18h Reserved
Bit
Type
Name
Default
Description
22:0
R/W
Reserved
144
Reserved
7.27 Reg 19h Reserved
Bit
Type
Name
Default
Description
4:0
R/W
Reserved
15
Reserved
7.28 Reg 1Ah Lock Detect Register
Bit
Type
Name
Default
Description
9:0
R/W
lkd_wincnt_max
298
threshold count in the timer window to declare
lock (reference cycles)
10
R/W
lkd_win_asym_enable
0
Enables asymmetric lock detect window
(nominal 10nsec)
11
R/W
lkd_win_asym_up_select
0
Sets polarity of the window
12
R/W
lkd_to_sdo_automux_en
1
Muxes the lkd output signal to SDO when SDO
is not being used for Main Serial Port Data
Outputs (Read Operation)
13
R/W
lkd_to_sdo_always
0
Muxes the lkd output signal to SDO always, not
possible to do Main Serial Port Read in this
state
14
R/W
lkd_ringosc_mono_select
0
1 select ringosc based oneshot for lock detect
window
0 selects analog based oneshot
