Design Guide
40 of 48
V 1.0
2018-06-06
XDPL8218 design guide
For high power factor flyback converter with constant voltage output
Fine-tuning guide
t
ZCDPD
parameter fine-tuning is, however, necessary to compensate for XDPL8218 internal propagation delay in
ZCD and also external delay caused by the noise-filtering capacitor at the ZCD pin.
recommended procedures for t
ZCDPD
parameter fine-tuning.
Table 14
Recommended procedures for t
ZCDPD
parameter fine-tuning
Step Instruction
I
Apply a differential probe on the board to measure the flyback MOSFET drain voltage waveform.
II
Set the t
ZCDPD
parameter to 0 and use the test configuration function in .dp Vision to power up the
board with low AC input voltage, e.g. 120 V
rms
, and full-load output.
If the board cannot be powered up, please refer to
Section 19
for the debugging guide.
III
Capture the waveform with a 1 ms time base and zoom into the voltage peak with a 1 µs time base.
IV
Place a horizontal cursor at the highest possible level which crosses two points on the resonance
part of the waveform (see a and b below), and measure the time between them (t
a-b
). In the
example below, which is based on the 40 W reference design, t
a-b
is measured to be approximately
744 ns.
V
Set the t
ZCDPD
parameter
as approximately half of t
a-b
and burn the configuration with .dp Vision.
VI
Disconnect the programming cable after burning, then power up the board and the flyback
MOSFET drain voltage waveform should be switching at the QRM1 (see example below based on
the 40 W reference design with fine-tuned t
ZCDPD
= 370 ns).
a
b
t
a-b
Zoom in at the peak
Zoom in at the peak
V
DRAIN
V
DRAIN
