Design Guide
23 of 48
V 1.0
2018-06-06
XDPL8218 design guide
For high power factor flyback converter with constant voltage output
Secondary-side regulation FB circuit design
Based on the above, R
bias,REF
= 6.2 kΩ is selected in this design example.
To achieve accurate output voltage regulation based on V
out,setpoint
, the op-amp input biasing current I
ib
has to be
much smaller than the output sensing upper resistor/divider current I
sense,SSR
. As compared to using the
conventional shunt regulator TL431, which has a maximum reference input current of 4 µA, the selected op-
amp has a maximum input bias current of I
ib,max
= 0.2 µA, which results in much lower regulation offset error
ERR
offset,ib
with the same level of I
sense,SSR
.
Considering that ERR
offset,ib
is desired to be not more than 0.1 percent in this design example, the maximum
output sensing upper divider resistance R
upper,max
can be de defined and calculated as:
𝑅
𝑢𝑝𝑝𝑒𝑟,𝑚𝑎𝑥
=
𝐸𝑅𝑅
𝑜𝑓𝑓𝑠𝑒𝑡,𝑖𝑏
∙ (𝑉
𝑜𝑢𝑡,𝑠𝑒𝑡𝑝𝑜𝑖𝑛𝑡
− 𝑉
𝑅𝐸𝐹
)
𝐼
𝑖𝑏,𝑚𝑎𝑥
=
0.1% ∙ (54 − 2.5)
0.2 ∙ 10
−6
= 257.5 𝑘Ω
(39)
Since the ABM burst frequency is fixed based on the f
burst
parameter for low audible noise, as a rule of thumb to
achieve stable main output voltage at no-load, the R
upper
selection should also ensure the output sensing
resistor/divider power consumption is at least the power transfer of a single ABM pulse. Therefore, the R
upper,max
value can also be defined and calculated as:
𝑅
𝑢𝑝𝑝𝑒𝑟,𝑚𝑎𝑥
=
𝐿
𝑝
∙ 𝑉
𝑜𝑢𝑡,𝑠𝑒𝑡𝑝𝑜𝑖𝑛𝑡
∙ (𝑉
𝑜𝑢𝑡,𝑠𝑒𝑡𝑝𝑜𝑖𝑛𝑡
− 𝑉
𝑅𝐸𝐹
)
𝑉
𝑖𝑛𝑂𝑉
2
∙ 𝑡
𝑜𝑛,𝑚𝑖𝑛,𝐴𝐵𝑀
2
∙ 𝑓
𝑏𝑢𝑟𝑠𝑡
∙ ƞ
𝐴𝐵𝑀
(40)
Where t
on,min,ABM
is the ABM minimum on-time parameter and
ƞ
ABM
is the estimated power efficiency in ABM.
Take f
burst
= 130 Hz, t
on,min,ABM
= 1 µs and assume
ƞ
ABM
= 65 percent,
𝑅
𝑢𝑝𝑝𝑒𝑟,𝑚𝑎𝑥
=
544 ∙ 10
−6
∙ 54 ∙ (54 −2.5)
350
2
∙ (1 ∙ 10
−6
)
2
∙ 130 ∙ 65%
= 146.15 𝑘Ω
Based on the smaller R
upper,max
calculated from equation (39) and (40), the output sensing upper resistance R
upper
should be selected near to R
upper,max
= 146.15 kΩ to achieve low standby power, so R
upper
= 127.5 kΩ is selected in
this design example.
The output sensing lower divider resistance R
lower
can then be defined and calculated as:
𝑅
𝑙𝑜𝑤𝑒𝑟
=
𝑅
𝑢𝑝𝑝𝑒𝑟
∙ 𝑉
𝑅𝐸𝐹
𝑉
𝑜𝑢𝑡,𝑠𝑒𝑡𝑝𝑜𝑖𝑛𝑡
− 𝑉
𝑅𝐸𝐹
=
127.5 ∙ 10
3
∙ 2.5
54 −2.5
(41)
𝑹
𝒍𝒐𝒘𝒆𝒓
≈ 𝟔. 𝟐 𝒌Ω
For good control-loop stability, the FB pin internal pull-up resistance parameter R
FB,pull,up
should be configured
not too high. On the other hand, for low standby power, R
FB,pull,up
should be configured not too low either. In a
practical system, R
FB,pull,up
may be around 5 kΩ. Hence, R
FB,pull,up
= 5.5 kΩ is selected in this design example.
XDPL8218’s internal ADC sampling point for the FB pin voltage signal is right after the GD pin signal becomes
high for a period of t
CS,LEB
(480 ns typ.), to ensure a high Signal to Noise Ratio (SNR). The FB pin capacitor C
FB
is
mainly used to filter the switching-on MOSFET current ringing noise, which might not be fully damped after
t
CS,LEB
. As the frequency of such ringing noise is normally at least a few MHz and the ADC sampling frequency
f
sampling,ADC
is a few kHz, the RC filter frequency f
RC,FB
formed by C
FB
and R
FB,pull,up
is recommended to be in the range
of 40 kHz to 100 kHz. Therefore, C
FB
can be defined and calculated as:
𝐶
𝐹𝐵
=
1
2 ∙ 𝜋 ∙ 𝑅
𝐹𝐵,𝑝𝑢𝑙𝑙,𝑢𝑝
∙ 𝑓
𝑅𝐶,𝐹𝐵
(42)
Taking f
RC,FB
= 60 kHz,
𝐶
𝐹𝐵
=
1
2 ∙ 𝜋 ∙ 5.5 ∙ 10
3
∙ 60 ∙ 10
3
= 482 pF
