Infineon XDPL8218, Руководство по конструкции

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Design Guide 10 of 48 V 1.0
2018-06-06
XDPL8218 design guide
For high power factor flyback converter with constant voltage output
CS resistor and GD pin-related design
5
CS resistor and GD pin-related design
Figure 5 shows the connections of the Current Sense (CS) resistor R
CS
, gate resistor R
G
and gate source resistor
R
GS
.
CS
R
CS
GD
R
GS
R
G
Figure 5 GD pin, CS pin, R
CS
, R
G
and R
GS
connections
Based on the CS pin voltage across R
CS
, the MOSFET current can be measured.
The recommended minimum CS resistor value R
CS,min
is defined and calculated as:
𝑅
𝐶𝑆,𝑚𝑖𝑛
=
0.45
𝐼
𝑝𝑟𝑖(𝑝𝑘),𝑚𝑎𝑥
=
0.45
2.606
= 0.173 Ω
(13)
The recommended maximum CS resistor value R
CS,max
is defined and calculated as:
𝑅
𝐶𝑆,𝑚𝑎𝑥
=
0.54
𝐼
𝑝𝑟𝑖(𝑝𝑘),𝑚𝑎𝑥
=
0.54
2.606
= 0.207 Ω
(14)
Based on the calculation results above, CS resistor R
CS
= 0.2 Ω is selected in this design example.
R
G
is to damp the gate-rise oscillaton, and R
GS
is to ensure the MOSFET remains in an off-state when AC input is
applied, with the IC not being activated yet. R
G
= 10 Ω and R
GS
= 20 kΩ are selected in this design example.
The gate-drive peak voltage V
GD,pk
is typically 12 V with sufficient V
CC
voltage supply. To achieve a good balance
of switching loss and EMI, the gate voltage rising slope can be controlled by configuring the gate driver peak
source current parameter I
GD,pk
(configurable range: 30 mA to 180 mA). This saves two components (see D
fastoff
,
R
slowon
in Figure 6 ), which are conventionally added for the same purpose.
t
V
GD
I
GD,pk
= 30mA
=118mA
(12V typ.)
I
GD,pk
V
GD,pk
Figure 6 Gate-drive voltage rising slope control with I
GD,pk
parameterization for component saving
With the high-speed switching characteristics of CoolMOS TM P7 MOSFET, it is recommended to configure the
I
GD,pk
parameter in the range of 30 mA to 49 mA.
As a result, I
GD,pk
= 30 mA is selected in this design example.