User Manual
97
Rev. 1.1
2019-03-18
TLE984xQX
Microcontroller with LIN and Power Switches for Automotive Applications
System Control Unit - Digital Modules (SCU-DM)
By setting bit OSC_CON.OSCWDTRST the oscillator watchdog can be restarted without a reset of the complete
PLL. The detection status output is only valid after some cycles of
f
INT
.
7.3.3.4
PLL VCO Lock Detection
The PLL has a lock detection that supervises the VCO part of the PLL in order to differentiate between stable
and instable VCO circuit behavior. The lock detector marks the VCO circuit and therefore the output
f
VCO
of the
VCO as instable if the two inputs
f
REF
and
f
DIV
differ too much. Changes in one or both input frequencies below
a level are not marked by a loss of lock because the VCO can handle such small changes without any problem
for the system.
shows values below that the lock is not lost for different input values.
7.3.3.5
Internal Oscillator (OSC_PLL)
The PLL internal oscillator is used for two different purposes:
Providing a Input Clock to the PLL
OSC_PLL operates at nominal frequency of 5 MHz.
The OSC_PLL can be used as input clock for all PLL modes. This is controlled and configured via
OSC_CON.OSCSS.
Operating the Oscillator Watchdog
The input frequency for the PLL direct from OSC_HP (XTAL), is supervised using the OSC_PLL as reference
frequency. For more information see
7.3.3.6
Switching PLL Parameters
The following restriction applies when changing PLL parameters via the PLL_CON register:
• Prescaler Mode (VCO bypass) may be enabled at any time, however, it has to be ensured that the maximum
operating frequency of the device f
sys
(see data sheet) will not be exceeded.
• Before switching NDIV, the Prescaler Mode has to be selected.
• K1DIV as well as K2DIV may be switched at any time, however, it has to be ensured that the maximum
operating frequency f
sys_max
of the device will not be exceeded.
• Only one parameter should be switched at one register write operation.
• Before switching the input clock source via OSC_CON.OSCSS, the Prescaler Mode has to be selected. Due
to a following potential oscillator watchdog event, the PLL may switch to Freerunning Mode. The
procedure to set up the PLL in normal operation follows that as stated in
• Before deselecting the Prescaler Mode, the PLL_CON.RESLD bit has to be set and then the LOCK flag has to
be checked. Only when the LOCK flag is set again, the Prescaler Mode may be deselected.
Note:
PDIV and NDIV can also be switched in Normal Mode. When changing NDIV, it must be regarded that
the VCO clock fVCO may exceed the target frequency until the PLL becomes locked. After changing
Table 39 Loss of VCO Lock Definition
Maximum Allowed Changing
d
f
DIV
/dt for
f
REF
=
(7.4)
0.8 MHz
1 MHz
1.25 MHz
≤
0.54
kHz/µs
≤
0.96
kHz/µs
≤
1.49
kHz/µs
