Infineon TLE984 QX Series, Руководство пользователя

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User Manual 482 Rev. 1.1
2019-03-18
TLE984xQX
Microcontroller with LIN and Power Switches for Automotive Applications
General Purpose Timer Units (GPT12)
External Count Clock Input
The external input signals of the GPT2 block are sampled with the GPT2 basic clock (see Figure 84 ). To ensure
that a signal is recognized correctly, its current level (high or low) must be held active for at least one complete
sampling period, before changing. A signal transition is recognized if two subsequent samples of the input
signal represent different levels. Therefore, a minimum of two basic clock periods are required for the
sampling of an external input signal. Thus, the maximum frequency of an input signal must not be higher than
half the basic clock.
Table 258 summarizes the resulting requirements for external GPT2 input signals.
These limitations are valid for all external input signals to GPT2, including the external count signals in
Counter Mode and the gate input signals in Gated Timer Mode.
16.4.7 Interrupt Control for GPT2 Timers and CAPREL
When a timer overflows from FFFF
H
to 0000
H
(when counting up), or when it underflows from 0000
H
to FFFF
H
(when counting down), its interrupt request flag in register GPT2_T5 or GPT2_T6I will be set. This will cause an
interrupt to the respective timer interrupt vector, if the respective interrupt enable bit is set.
Table 257 GPT2 Timer Parameters
System Clock = 10 MHz Overall
Divider
Factor System Clock = 40 MHz
Frequency Resolution Period Frequency Resolution Period
5.0 MHz 200 ns 13.11 ms 2 20.0 MHz 50 ns 3.28 ms
2.5 MHz 400 ns 26.21 ms 4 10.0 MHz 100 ns 6.55 ms
1.25 MHz 800 ns 52.43 ms 8 5.0 MHz 200 ns 13.11 ms
625.0 kHz 1.6 µs 104.9 ms 16 2.5 MHz 400 ns 26.21 ms
312.5 kHz 3.2 µs 209.7 ms 32 1.25 MHz 800 ns 52.43 ms
156.25 kHz 6.4 µs 419.4 ms 64 625.0 kHz 1.6 µs 104.9 ms
78.125 kHz 12.8 µs 838.9 ms 128 312.5 kHz 3.2 µs 209.7 ms
39.06 kHz 25.6 µs 1.678 s 256 156.25 kHz 6.4 µs 419.4 ms
19.53 kHz 51.2 µs 3.355 s 512 78.125 kHz 12.8 µs 838.9 ms
9.77 kHz 102.4 µs 6.711 s 1024 39.06 kHz 25.6 µs 1.678 s
4.88 kHz 204.8 µs 13.42 s 2048 19.53 kHz 51.2 µs 3.355 s
Table 258 GPT2 External Input Signal Limits
GPT2 Basic Clock = 10 MHz Input
Frequ.
Factor GPT2
Divider
BPS2 Input Phase
Duration GPT2 Basic Clock = 40 MHz
Max. Input
Frequency Min. Level
Hold Time Max. Input
Frequency Min. Level
Hold Time
2.5 MHz 200 ns f
GPT
/4 01
B
2 × t
GPT
10.0 MHz 50 ns
1.25 MHz 400 ns f
GPT
/8 00
B
4 × t
GPT
5.0 MHz 100 ns
625.0 kHz 800 ns f
GPT
/16 11
B
8 × t
GPT
2.5 MHz 200 ns
312.5 kHz 1.6 µs f
GPT
/32 10
B
16 × t
GPT
1.25 MHz 400 ns