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Application Note 

18 of 19 

001-87564 Rev.*D  

 

 

2021-06-01 

A Design Guide to SPI F-

RAM™ Processor Companion 

- FM33256B 

Revision history 

r e s t r i c t e d  

Revision history

 

Document 
version 

Date of release 

Description of changes 

** 

2013-06-25 

New Spec. 

*A 

2014-11-17 

Added PSoC 3-based User Module project 
Replaced Pseudo codes with PSoC 3-based application code. 
Rewording / typo fixes 

*B 

2016-06-02 

Added a reference to code example CE204087 
Updated template  

*C 

2017-07-07 

Updated logo and copyright. 

*D 

2021-06-01 

Migrated to IFX template. 

Содержание SPI F-RAM FM33256B

Страница 1: ...the users of SPI F RAMTM processor companion FM33256B Table of contents About this document 1 Table of contents 1 1 Introduction 2 2 Two Logical Devices in One 3 3 Typical Application 4 4 Processor Companion Features 5 4 1 System Power On Reset with RST pin 5 4 2 Early Power Fail Warning 6 4 3 Event Counter 6 4 4 Serial Number 7 5 Real Time Clock 8 5 1 Backup Power 9 5 2 RTC Calibration 9 5 2 1 Se...

Страница 2: ...The processor companion section includes a power on system reset low voltage detect a watchdog timer an early power fail warning an event counter automatic switchover to backup power and a lockable 64 bit serial number It employs an industry standard SPI which is used to access the memory the processor companion and the RTC The FM33256B operates over a 2 7 V to 3 6 V power supply range with the ma...

Страница 3: ...o Logical Devices with Unique Opcodes The memory is one logical device and the companion RTC is the other logical device This helps to integrate both the functionalities without affecting each other Each has its own address space and is accessed via the SPI The F RAM is accessed through the standard memory opcodes 0x02 for Write and 0x03 for Read The processor companion RTC is accessed through spe...

Страница 4: ...ith a microcontroller the FM33256B device and other passive components The example microcontroller has a dedicated SPI port All microcontrollers may not have this port in such cases the SPI protocol may be implemented in firmware and bit banged through GPIO pins Note Bit banging is a technique used for serial communications It uses firmware instead of a dedicated hardware Firmware directly sets an...

Страница 5: ...d its nominal operating value The point at which the RST pin is released is determined by VTP Voltage Trip Point an internal trip voltage that is always compared to VDD The internal pull up resistor approximately 150 kΩ on the RST pin eliminates the need for an external resistor When tripped the reset circuit times out after approximately 65 ms 30 ms minimum 100 ms maximum You may set VTP 2 bits V...

Страница 6: ... Power Fail Interrupt using the F RAM Processor Companion 4 3 Event Counter The FM33256B device integrates a 16 bit event counter for tamper detection or other event logging purposes The counter has an input pin CNT that is edge triggered and polarity that is user defined The event or edge must be CMOS logic level The counter control register is nonvolatile and counter values are either battery ba...

Страница 7: ...pin is set to polled mode which occasionally samples the pin in order to minimize the battery drain There are no external resistors required for this case The event counter is configured to detect a rising edge CP 1 register 0Dh bit 0 on the CNT pin When the switch is open a tamper event is registered and the counter increments 4 4 Serial Number The F RAM processor companion provides a 64 bit lock...

Страница 8: ...he RTC the OSCEN bit register 00h bit 7 must first be set to 0 Then the clock and calendar registers must be written to reflect the current time day and date The RTC register map is shown in Figure 4 Figure 4 RTC Register Map The 32 768 kHz oscillator is divided down through a series of counters The first counter divides it by 32 768 to derive the 1 Hz signal for the seconds counter The next count...

Страница 9: ...backup data To avoid this situation the charge on the capacitor needs to be restored For different types of charging refer to AN401 Charging Methods for the F RAM RTC Backup Capacitor 5 2 RTC Calibration RTC calibration is required primarily to compensate the frequency shift due to crystal tolerance temperature effect and load capacitance mismatch A 512 Hz signal brought out on the ACS Alarm Calib...

Страница 10: ...t pin that drives the FM33256B CS Chip Select pin As the system microcontroller powers up its outputs will tristate before the power supply reaches sufficient voltage to turn various internal circuits on thereby allowing the pull up resistor to keep the signal at VDD Similarly at power down the VDD voltage reaches a point where it allows the outputs to let go again allowing the pull up resistor to...

Страница 11: ...plication Notes AN407 A Design Guide to I2C F RAM Processor Companions FM31278 FM31276 FM31L278 and FM31L276 AN400 Generating a Power Fail Interrupt using the F RAM Processor Companion AN401 Charging Methods for the F RAM RTC Backup Capacitor AN402 F RAM RTC Oscillator Design Guide AN404 F RAM RTC Backup Supply VBAK pin and UL Compliance 9 PSoC 3 User Module The PSoC 3 based user module project to...

Страница 12: ...emory data out Reads data from F RAM array WRDI 0000_0100b Clears WEL RDSR 0000_0101b Status Register data out Read WPEN BP 1 0 WEL bits WRSR 0000_0001b Status Register data in Write WPEN and BP 1 0 bits RDPC 0001_0011b 1 byte Register data out Companion RTC register read WRPC 0001_0010b 1 byte Register data in Companion RTC register write define nvRAM_WREN 0x06 define nvRAM_RTC_WRITE_CMD 0x12 def...

Страница 13: ... data 1 0x10 Minutes set to 10 data 2 0x14 Hours set to 14 2 PM data 3 0x03 Day set to the third day of the week data 4 0x04 Date set to the fourth day in March data 5 0x03 Month set to March data 6 0x08 Year set to 2008 WRITE_RTC 0x02 Sets the address pointer to Register 02h data Writes time date 0x07 Number of bytes to be written RTC does not start to run yet Step 3 Clear W bit to start RTC with...

Страница 14: ...TC Registers Read RTC Registers Step 1 Set R bit which takes snapshot of RTC registers data 0 0x01 Data for setting the R bit WRITE_RTC 0x00 Sets the address pointer to Register 00h data Writes data 0x01 which sets the R bit 0x01 Number of bytes to be written Step 2 Read RTC Registers READ_RTC 0x02 Sets the address pointer to Register 02h data Data buffer to read RTC registers 0x07 Number of bytes...

Страница 15: ...ter 0Dh data Writes data 0x09 which sets the R bit 0x01 Number of bytes to be written Step 2 Read Event Counter READ_RTC 0x0E Sets the address pointer to Register 0Dh data Data buffer to read RTC registers 0x02 Number of bytes to be read data buffer contains the following 0x1A CounterByte0 reads out LSB 0x1A decimal 26 0x00 CounterByte1 reads out MSB 0x00 Step 3 Clear RC bit data 0 0x01 data 0x01 ...

Страница 16: ...SPI_1_SPIM_STS_SPI_DONE nvRAM_SPI_1_SPIM_STS_SPI_DONE Make chip select High CS 1 nvRAM_SPI_1_CS_Reg_Write 1 Delay CyDelay 1 Clear the Transmit Buffer nvRAM_SPI_1_SPIM_ClearTxBuffer Make chip select LOW CS 0 nvRAM_SPI_1_CS_Reg_Write 0 Send Processor Companion Write Command nvRAM_SPI_1_SPIM_WriteTxData nvRAM_RTC_WRITE_CMD Send Processor Companion Register address nvRAM_SPI_1_SPIM_WriteTxData uint8 a...

Страница 17: ...nion Read Register Address nvRAM_SPI_1_SPIM_WriteTxData uint8 addr Wait for the transfer to complete while nvRAM_SPI_1_SPIM_ReadTxStatus nvRAM_SPI_1_SPIM_STS_SPI_DONE nvRAM_SPI_1_SPIM_STS_SPI_DONE Read the data and store in data_read_ptr for i 0 i total_data_count i Clear receive buffer nvRAM_SPI_1_SPIM_ClearRxBuffer Send a dummy byte nvRAM_SPI_1_SPIM_WriteTxData uint8 0x00 Wait for the transfer t...

Страница 18: ...Document version Date of release Description of changes 2013 06 25 New Spec A 2014 11 17 Added PSoC 3 based User Module project Replaced Pseudo codes with PSoC 3 based application code Rewording typo fixes B 2016 06 02 Added a reference to code example CE204087 Updated template C 2017 07 07 Updated logo and copyright D 2021 06 01 Migrated to IFX template ...

Страница 19: ...ntellectual property rights of any third party with respect to any and all information given in this application note The data contained in this document is exclusively intended for technically trained staff It is the responsibility of customer s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in th...

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