Infineon SPI F-RAM FM33256B, Руководство пользователя

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Application Note 16 of 19 001-87564 Rev.*D
2021-06-01
A Design Guide to SPI F- RAM™ Processor Companion - FM33256B
Pseudo Code Examples
r e s t r i c t e d
10.6 SPI Processor Companion Write
/********PSoC3 Based Pseudo Code for SPI Processor Companion Write ********/
uint8 WRITE_RTC ( uint8 addr, uint8 *data_write_ptr, uint8 total_data_count)
{
uint8 i;
// Clear the Transmit Buffer
nvRAM_SPI_1_SPIM_ClearTxBuffer();
// Send Write Enable WREN command
// Make chip select LOW CS = 0
nvRAM_SPI_1_CS_Reg_Write(0);
// Send Write Enable Command WREN
nvRAM_SPI_1_SPIM_WriteTxData(nvRAM_WREN);
// Wait for the transfer to complete
while((nvRAM_SPI_1_SPIM_ReadTxStatus() & nvRAM_SPI_1_SPIM_STS_SPI_DONE) !=
nvRAM_SPI_1_SPIM_STS_SPI_DONE);
// Make chip select High CS = 1
nvRAM_SPI_1_CS_Reg_Write(1);
// Delay
CyDelay(1);
// Clear the Transmit Buffer
nvRAM_SPI_1_SPIM_ClearTxBuffer();
// Make chip select LOW CS = 0
nvRAM_SPI_1_CS_Reg_Write(0);
// Send Processor Companion Write Command
nvRAM_SPI_1_SPIM_WriteTxData(nvRAM_RTC_WRITE_CMD);
// Send Processor Companion Register address
nvRAM_SPI_1_SPIM_WriteTxData((uint8)(addr));
// Wait for the transfer to complete
while((nvRAM_SPI_1_SPIM_ReadTxStatus() & nvRAM_SPI_1_SPIM_STS_SPI_DONE) !=
nvRAM_SPI_1_SPIM_STS_SPI_DONE);
// Send Processor Companion Register data
for(i = 0; i < total_data_count; i++ )
{
nvRAM_SPI_1_SPIM_WriteTxData((uint8)(data_write_ptr[i]));
while((nvRAM_SPI_1_SPIM_ReadTxStatus() & nvRAM_SPI_1_SPIM_STS_SPI_DONE)
!=
nvRAM_SPI_1_SPIM_STS_SPI_DONE);
}
// Make chip select HIGH CS = 1
nvRAM_SPI_1_CS_Reg_Write(1);
}