Application Note
29 of 53
V 1.0
2019-04-01
IM393 Application note
IM393 IPM Technical Description
Function and protection circuit
It is also important to note that C
RCIN
needs to be minimized in order to make sure it is fully discharged in the
event of over-current. Since the ITRIP pin has a 350 ns input filter, it is appropriate to ensure that C
RCIN
will be
discharged below V
IN_TH-
by the open-drain MOSFET, after 350 ns. Therefore, the max C
RCIN
can be calculated as:
V
RFE
(t) = 3.3 V * e
-t/RC
< V
IN_TH-
(6)
C
RCIN
< 350 ns / (- ln (V
IN_TH-
/ 3.3 V) * R
RFE_ON
)
(7)
Considering V
IN_TH-
of 0.8 V and R
RFE_ON
of 50 Ω, C
RCIN
should be less than 4.9 nF.
In the case of 5 V,
V
RFE
(t) = 5 V * (1 – e
-t/RC
)
(8)
T
FLT-CLR
= - R
RCIN
* C
RCIN
* ln (1-V
IN_TH+
/5 V)
(9)
For example, if R
RCIN
is 1.2 MΩ and C
RCIN
is 1 nF, the T
FLT-CLR
is about 0.8 ms with V
IN_TH+
of 2.5 V.
The max C
RCIN
can be calculated as:
V
RFE
(t) = 5 V * e
-t/RC
< V
IN_TH-
(10)
C
RCIN
< 350 ns / (- ln (V
IN_TH-
/ 5 V) * R
RFE_ON
)
(11)
Considering V
IN_TH-
of 0.8 V and R
RFE_ON
of 50 Ω, C
RCIN
should be less than 3.8 nF.
As far as R
RCIN
is concerned, it should be selected to achieve the desired T
FLT-CLR
. Its value should not be too low to
interfere with the discharging of C
RCIN
in the case of over-current. Also it cannot be too high in order to ensure
proper biasing of the RFE pin during normal operation. A resistor value between 0.5 MΩ and 2 MΩ is suggested to
have a fault-clear time in the range of 1 ms.
It is critical that the PWM generator be disabled within the fault duration to guarantee a shutdown of the system,
and the over-current condition must be cleared before resuming operation.
5.3
Undervoltage lockout (UVLO)
IM393-XX HVIC provides undervoltage lockout protection on both the V
DD
(logic and low-side circuitry) power
supply and the V
BS
(high-side circuitry) power supply. Figure 20 is used to illustrate this concept. V
DD
or V
BS
is
plotted over time, and as the waveform crosses the UVLO threshold (V
DDUV+/-
or V
BSUV+/-
), the undervoltage
protection is enabled or disabled.
Upon power-up, should the V
DD
voltage fail to reach V
DDUV+
threshold, the IC will not turn on. Additionally, if the
V
DD
voltage decreases below the V
DDUV-
threshold during operation, the undervoltage lockout circuitry will
recognize a fault condition, and shut down the high and low-side gate drive outputs. The RFE pin will then go to
the low state to inform the controller of the fault condition.
Upon power-up, should the V
BS
voltage fail to reach the V
BSUV+
threshold, the IC will not turn on. Additionally, if
the V
BS
voltage decreases below the V
BSUV-
threshold during operation, the undervoltage lockout circuitry will
recognize a fault condition, and shut down the high-side gate drive outputs of the IC.
The UVLO protection ensures that the IC drives the power devices only when the gate supply voltage is
sufficient to fully enhance the power devices. Without this feature, the power switch could be driven with a low
gate voltage which results in excessive losses, as it conducts current while the channel impedance is high.
When conduction losses are too high within the power switch, it could lead to power switch failure.