Infineon IDP2303, Руководство по конструкции

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Design guide IDP2303(A)
Introduction
Application Note 4 Revision 2.0
2017-05-03
2 Introduction
2.1 IC Introduction
The IDP2303(A) is a multi-mode PFC and LLC controller combined with a floating high side driver and a
startup cell. A digital engine provides advanced algorithms for multi-mode operation to support the highest
efficiency over the whole load range. A comprehensive and configurable protection feature set is
implemented. Only a minimum of external components are required. The integrated HV startup cell and
advanced burst mode enable the achievement of low stand-by power. In addition, a one-time-programming
(OTP) unit is integrated to provide a wide set of configurable parameters that help to ease the design in
phase of the project. [1][2].
2.2 Pin configuration and description
The pin configuration is shown in Figure 1 and Table 1.
Figure 1
Pin configuration
Table 1
Pin definitions and functions
Symbol Pin Type Function
GD0
(PFCGD)
1 O Gate driver output 0 (PFC gate driver)
Output for directly driving the PFC PowerMOS. The default peak source current
capability is 156 mA and the peak sink current capability is 800 mA.
CS0
(PFCCS)
2 I Current sense 0 (PFC current sense)
Pin CS0 is connected to an external shunt resistor and the source of the PFC
PowerMOS.
VCC 3 P Positive voltage supply
IC power supply
GND 4 G Ground
IC ground
ZCD 5 I Zero crossing detection
Pin ZCD is connected to the auxiliary winding of the PFC choke.
1
2
3
4
14
15
16
HSGND
GD0
HSVCC
VCC
HSGD
GND
13
N.C.
5
6
7
8
10
11
12
HBFB
ZCD
CS1
N.C.
GD1
HV
9
MFIO
VS
CS0
ID
P
2
3
0
3
PG-DSO-16 (150mil)