Design guide IDP2303(A)
PFC design
Application Note
19
Revision 2.0
2017-05-03
It can be seen from the calculation that the actual tolerance of current and power can be very high. Methods
to reduce tolerances include:
Reduce the tolerance of the shunt resistor
Reduce the tolerance of the PFC choke
Reduce the value of R and C for the RC filter to reduce the delay
The above calculation is accurate, but is relatively complicated, and requires input data from actual
measurements on a real power board (e.g. external propagation delay). A faster and simpler way to obtain a
value for the current sense resistor is for customers to use the spreadsheet calculation to finalize the value
after the power board is built.
𝑅
𝑃𝐹𝐶_𝐶𝑆
<
𝑉
𝑂𝐶𝑃_𝑃𝐹𝐶
∗ (1 − 𝑔
𝑒𝑟𝑟𝑜𝑟
) ∗ 𝑔
𝑓𝑖𝑙𝑡𝑒𝑟
𝐼
𝑝𝑘
∗ (1 − ∆
𝑑𝑒𝑙𝑎𝑦
)
=
0.6 ∗ 0.94 ∗ 0.9
4.39 ∗ (1 − 0.1)
= 0.13 𝛺
Where
𝑔
𝑒𝑟𝑟𝑜𝑟
is the OCP threshold gain error,
𝑔
𝑓𝑖𝑙𝑡𝑒𝑟
is the gain of RC filter and
∆
𝑑𝑒𝑙𝑎𝑦
is the estimated error
due to the internal and external propagation delay.
3.3.4.2
Verification of PFC inductance with OCP tolerance
The maximum peak current allowed by the OCP (considering the tolerance) can be obtained from the
spreadsheet calculation results and then applied to the equation below to verify the B
max
of the PFC
inductance:
𝐵
𝑚𝑎𝑥
=
𝑖
𝑝𝑘
∗ 𝐿
𝑃𝐹𝐶
𝑁
𝑃𝐹𝐶
𝐴
𝑚𝑖𝑛
=
6.7 ∗ 200
39 ∗ 99
= 0.34 𝑇
This value is less than the saturation magnetic flux density (B) of 0.35 T (PC40 magnetic material). Therefore,
the PFC choke will not saturate under worst case conditions.
3.3.5
Frequency law for multi-mode PFC
3.3.5.1
Multimode PFC
For a PFC circuit operating in Critical Conduction Mode (CrCM), the MOSFET is turned on with a constant on-
time throughout the complete AC half cycle and the off-time varies during the AC half cycle depending on
the instantaneous input voltage applied. A new switching cycle starts just after the inductor current reaches
zero. CrCM is also equivalent to quasi-resonant switching at the first inductor current valley or QR1
operation.
CrCM is ideal for full load operation, where the constant on-time is large. However, the constant on-time
reduces at light load, resulting in very high switching frequency - particularly near the zero crossings of the
input voltage. The high switching frequency will increase the switching losses, resulting in poor efficiency at
light load.
The multimode PFC control can lower the switching frequency by adding an additional delay (
𝑡
𝑤
) into each
switching cycle through selecting further inductor current valleys (matching also with valleys of
V
DS
of
MOSFET) to achieve QR2, QR3 and up to QR10 operation. Figure 13 illustrates the QR2 valley switching in
multimode PFC control as an example.
