PSoC 4 Down Counter 7-bit
Document No. 002-24891 Rev.**
2
Design and Implementation
The Count7 timer period can be varied. In this example, Count7 is configured with a period of 128, so the first count is 127 and
Count7 resets when it reaches 0. A kit button and a control register are used to enable the counter, as
status register allows for reading of the counter output.
Firmware does the following:
1. Starts the UART and Count7 operation.
2. Configures interrupt handler Switch_InterruptHandler.
3. Before obtaining the current value of the counter, the counter is stopped. The counter is restarted after getting a copy of the
count.
4. The counter is read directly, and its digital outputs are read via the status register. If either value has changed, the UART
displays both values. The two values should always be the same.
When the button is pressed, Switch_ISR interrupt occurs, Switch_InterruptHandler is called, and the Control register output is
toggled.
Figure 2. PSoC Creator Project Schematic
Components and Settings
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lists the PSoC Creator Components used in this example, how they are used in
the design, and the non-default settings required so they function as intended.
Table 1. PSoC Creator Components
Component
Instance Name
Purpose
Non-default Settings
Down Counter (7-bit) [v1.0]
Count7
Implements the down counter functionality
Set
EnableSignal
to Enabled
Control Register [v1.80]
Control_Reg
Allows for digital signal outputs
Set
Outputs
to 1
Status Register [v1.90]
Status_Reg
Allows for digital signals to be read
Set
Inputs
to 7
Digital Input Pin [v2.20]
Switch_pin
Handles the SW2 connection on the device
See
UART (SCB mode) [v4.0]
UART
Handles UART communication
None
Interrupt [v1.70]
Switch_ISR
Handles Interrupt
None
