Infineon AIROC CYW20835 Скачать руководство пользователя страница 5

  

User Guide 

5 of 11 

002-34024 Rev. **  

 

 

2021-10-05 

 

AIROC™ CYW20835 Bluetooth® LE system on chip hardware design 

guidelines 

 

Component placement 

 

2.4

 

Decoupling capacitors

 

See the reference schematic for decoupling capacitor usage and values on different power domains. Infineon 
recommends that you use the vendor and part numbers shown in the reference design BOM. Decoupling 
capacitors must be placed as close to its associated pin as possible. 

2.5

 

Ground vias

 

Do not use long thin traces to connect components to ground vias; doing so adds inductance that can 
significantly alter circuit performance.  

2.6

 

Bandpass filter

 

Place a chip bandpass filter between the antenna matching components and the CYW20835 device to attenuate 
harmonics from CYW20835. The chip band pass filter part used in the CYW20835 reference design is Murata, 
LFB182G45CL3D178.A microstrip is used for all connections of the bandpass filter. 

Insertion loss and out

of

band attenuation performance depend on PCB component layouts and tolerances. 

Filter layout should follow general RF layout rules. 

2.7

 

Analog mic signals

 

Place a series 0.1-µF capacitor for each of the analog MIC signals, MIC_P and MIC_N. MIC_P and MIC_N should 
also be routed within the analog ground (GND_A) area as shown in 

Figure 3

. Use net ties to shown i

Figure 3

 

to stitch GND_A to the main ground. The analog MIC is powered by the CYW20835

’s MIC_BIAS pad by default.

 

 

 

Figure 3

 

Bandpass filter and decoupling capacitors 

Содержание AIROC CYW20835

Страница 1: ...tem on chip hardware design guidelines About this document This document discusses the hardware design guidelines for the AIROC CYW20835 Bluetooth LE system on chip kit Scope and purpose This document provides basic guidelines on layout for AIROC CYW20835 Bluetooth LE system on chip Intended audience This document provides hardware guidance on how to design with CYW20835 ...

Страница 2: ... layout guidelines 3 2 Component placement 4 2 1 Antenna placement 4 2 2 PCB antenna 4 2 3 Crystal placement 4 2 4 Decoupling capacitors 5 2 5 Ground vias 5 2 6 Bandpass filter 5 2 7 Analog mic signals 5 2 8 Serial flash 6 2 9 Layer 2 solid ground fill 6 2 10 Power traces 6 2 11 Avoid routing DC power in a loop 6 2 12 Power inductor 7 2 13 Layer 4 8 2 14 Assembly instructions 9 Revision history 10...

Страница 3: ...erence ground layer selections two things should be considered 1 Thinner traces have higher insertion loss PCB fabrication requires adequate trace width for reliability and repeatability The heights between the microstrip and ground should be thick enough to guarantee adequate trace width for the microstrip 2 For microstrip lines avoid sharp corners use a smooth radius to change directions The cop...

Страница 4: ...equate ground clearance for the layers beneath theantenna In the reference design the antenna is on the top layer on the left of the board next to the CYW20835 chip 2 2 PCB antenna For more details on PCB antennas see AN91445 Antenna design and RF layout guidelines For the associated Gerber file visit https www cypress com go AN91445 Figure 2 Antenna placement and microstrip clearance 2 3 Crystal ...

Страница 5: ...p bandpass filter between the antenna matching components and the CYW20835 device to attenuate harmonics from CYW20835 The chip band pass filter part used in the CYW20835 reference design is Murata LFB182G45CL3D178 A microstrip is used for all connections of the bandpass filter Insertion loss and out of bandattenuationperformancedepend on PCB component layouts and tolerances Filter layout should f...

Страница 6: ...C is necessary The GND_A cutout should cover all of the analog MIC signal and power traces on Layer 1 Figure 4 Layer 2 solid ground fill 2 10 Power traces Use wide traces for power supply lines You should calculate the maximumcurrent to be carried on each trace and make the trace width proportionateto the current Route the main DC power supply line up the middle of the board like a spine branching...

Страница 7: ...dth VPA_BT Minimum 12 mils trace width PALDO_VDDOUT3V pin 20 to BT_PAVDD2P5 pin 26 Minimum 8 mils trace width 1P2VRF Minimum 8 mils trace width 1P2VRF to IFVDD1P2 pin 19 PLLVDD1P2 pin 21 VCOVDD1P2 pin 20 Minimum 8 mils trace width MIC_AVDD pin 48 Minimum 8 mils trace width MIC_BIAS pin 45 Minimum 8 mils trace width Figure 5 Power supply traces 2 12 Power inductor Ensure that there is ground isolat...

Страница 8: ...2 34024 Rev 2021 10 05 AIROC CYW20835 Bluetooth LE system on chip hardware design guidelines Component placement Figure 6 Power inductor routing 2 13 Layer 4 Use Layer 4 for all non critical signal routing Figure 7 Layer 4 ...

Страница 9: ...em on chip hardware design guidelines Component placement 2 14 Assembly instructions CYW20835 is an Infineon standard QFN quad flat no lead package For additional assembly instructions and reflow profiles see AN72845 Design guidelines for quad flat no lead QFN packaged devices ...

Страница 10: ...1 002 34024 Rev 2021 10 05 AIROC CYW20835 Bluetooth LE system on chip hardware design guidelines Revision history Revision history Major changes since the last revision Date Version Description 2021 10 05 Initial release ...

Страница 11: ...d any applicable legal requirements norms and standards concerning customer s products and any use of the product of Infineon Technologies in customer s applications The data contained in this document is exclusively intended for technically trained staff It is the responsibility of customer s technical departments to evaluate the suitability of the product for the intended application and the com...

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