Infineon AIROC CYW20835, Руководство пользователя, Страница: 3 / 11

User Guide 3 of 11 002-34024 Rev. **
2021-10-05
AIROC™ CYW20835 Bluetooth® LE system on chip hardware design
guidelines
Basic layout guidelines
1 Basic layout guidelines
Most Bluetooth® devices use four
‐
layer boards to minimize thickness. Components are placed on the top layer;
the bottom layer is a solid ground fill. Most signal traces are routed on the top layer.
For RF traces, use a 50
‐
ohm transmission line to minimize mismatch losses and reflections, and therefore
maximize the power transferred to the load.
There are two types of transmission lines: microstrip and stripline. The reference design uses the microstrip
design.
Transmission lines require a proper geometry. Some parameters are highly dependent on the dielectric
material
– trace width, vertical distance to ground plane, and a solid ground plane of sufficient width. Different
height and width solutions perform differently.
For the microstrip layer and its reference ground layer selections, two things should be considered:
1. Thinner traces have higher insertion loss – PCB fabrication requires adequate trace width for reliability and
repeatability. The heights between the microstrip and ground should be thick enough to guarantee
adequate trace width for the microstrip.
2. For microstrip lines, avoid sharp corners; use a smooth radius to change directions. The coplanar ground
follows the contour of these traces with a clearance of two to three line widths (2 W to 3 W). Connect the
outer layer to the reference ground plane using vias so that they surround the microstrip trace.
The microstrip is used in this reference design is on Layer 1. The reference ground is Layer 2. This reference
design uses a four
‐
layer PCB with a stack up as shown in Figure 1 .
•
Layer 1: Main signal layer
•
Layer 2: Solid ground layer
•
Layer 3: Power signal layer
•
Layer 4: Digital signal layer. Additional power signals that could not be routed on Layer 3 can be routed here
as well. However, you must ensure that they do not overlap any of the power signals on Layer 3.
Figure 1 Typical board stackup used for CYW20835