IEI Technology PCISA-MARK, Руководство пользователя

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PCISA-MARK CPU Card
DRAM Timing by SPD [Enabled]
Use the DRAM Timing by SPD option to enable the system to use the SPD ( Serial
Presence Detect) EEPROM to configure the DRAM timing. The SPD EEPROM contains
all necessary DIMM specifications including speed of the individual components such as
CAS (column array strobe) and bank cycle time as well as valid settings for the module
and the manufacturer's code. The SPD enables the BIOS to read the spec sheet of the
DIMM on boot-up and then adjust the memory timing parameters accordingly.
Disabled DRAM timing parameters can be manually set using
the DRAM sub-items
Enabled (D
EFAULT
) DRAM timing parameter are set according to the
DRAM Serial Presence Detect (SPD)
If the Configure DRAM Timing by SPD option is disabled, the following configuration
options appear.
DRAM Clock
SDRAM Cycle Length
Bank Interleave
DRAM Clock [Host CLK]
Use the DRAM Clock option to select the RAM FSB.
Host CLK (D
EFAULT
) RAM FSB is 100MHz
HCLK-133M RAM FSB is 133MHz
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