PCIE-Q350 PICMG 1.3 CPU Card
Page 57
CN Location:
See Figure 4-4
CN Pinouts:
See Table 4-5
The digital input/output connector is managed through a Super I/O chip. The DIO
connector pins are user programmable. To see details on how to program the DIO chip,
please refer to
Appendix B
.
Figure 4-4: DIO Connector Connector Locations
Содержание PCIE-Q350
Страница 23: ...PCIE Q350 PICMG 1 3 CPU Card Page 2 1 Introduction Chapter 1...
Страница 30: ...PCIE Q350 PICMG 1 3 CPU Card Page 9 2 Detailed Specifications Chapter 2...
Страница 33: ...PCIE Q350 PICMG 1 3 CPU Card Page 12 Figure 2 3 Data Flow Block Diagram...
Страница 66: ...PCIE Q350 PICMG 1 3 CPU Card Page 45 3 Unpacking Chapter 3...
Страница 71: ...PCIE Q350 PICMG 1 3 CPU Card Page 50 4 Connector Pinouts Chapter 4...
Страница 86: ...PCIE Q350 PICMG 1 3 CPU Card Page 65 Figure 4 9 Keyboard Mouse Connector Location...
Страница 99: ...PCIE Q350 PICMG 1 3 CPU Card Page 78 5 Installation Chapter 5...
Страница 128: ...PCIE Q350 PICMG 1 3 CPU Card Page 107 6 BIOS Screens Chapter 6...
Страница 175: ...PCIE Q350 PICMG 1 3 CPU Card Page 154 7 Software Drivers Chapter 7...
Страница 219: ...PCIE Q350 PICMG 1 3 CPU Card Page 198 A BIOS Options Appendix A...
Страница 223: ...PCIE Q350 PICMG 1 3 CPU Card Page 202 B DIO Interface Appendix B...
Страница 226: ...PCIE Q350 PICMG 1 3 CPU Card Page 205 C Watchdog Timer Appendix C...
Страница 229: ...PCIE Q350 PICMG 1 3 CPU Card Page 208 D Intel Matrix Storage Manager Appendix D...
Страница 243: ...PCIE Q350 PICMG 1 3 CPU Card Page 222 E Hazardous Materials Disclosure Appendix E...
Страница 247: ...PCIE Q350 PICMG 1 3 CPU Card Page 226 F Compatibility Appendix G...