5
©2018 Integrated Device Technology, Inc.
August 30, 2018
VersaClock
®
6E Family Register Descriptions and Programming Guide
OTP Programming
The steps for OTP programming are given in
. The procedure is to write the desired default data to the appropriate RAM registers,
and then to instruct the part to burn a desired register address range into OTP.
The RAM registers have an 8-bit register address (0x00 to 0x9F), while the user OTP registers have a 9-bit address (0x000 to 0x177).
This is because there are 4 banks of configuration data in OTP. The OTP addressing therefore extends across two RAM registers (
). The 9-bit user start address is set by register 0x73[7:0] + 0x74[7]. The 9-bit user end address is set by register 0x75[7:0] + 0x76[7].
Table 5. OTP Programming Procedure
Step
Procedure
Notes
0
Connect all VDD pins to a single 3.3V, with OUT0_SEL_I2CB pin
left floating.
Power on the part in I²C mode.
1
Wait 100ms.
Part power-up initialization.
2
Write device RAM configuration registers 0x10 to 0x69 to the
desired state.
These RAM values will be programmed into OTP as new
default register values.
3
Write registers 0x73 to 0x78 following the procedure in Table 5.
Set burn register source address range and destination register
bank CFG0, 1, 2, or 3.
4
Write register 0x72 = 0xF0.
Reset burn bit.
5
Write register 0x72 = 0xF8.
Burn the OTP range defined above.
6
Wait 500ms.
Wait for burn to complete. Device stops acknowledging while
burning.
7
Write register 0x72 = 0xF0.
Reset burn bit.
8
Write register 0x72 = 0xF8.
Repeat the burn.
9
Wait 500ms.
Wait for burn to complete. Device stops acknowledging while
burning.
10
Write register 0x72 = 0xF0.
Reset burn bit.
11
Done programming.
Programming complete.
12
Write register 0x72 = 0xF2.
Perform margin read.
13
Write register 0x72 = 0xF0.
Reset margin read bit.
14
Read register 0x9F:
If bit D1 = 0, programming was successful.
If bit D1 = 1, programming failed.
Test if OTP programming was successful.
15
Write register 0x9F = 0x00.
Reset margin read status bit.
16
One configuration register bank (CFG0, 1, 2, or 3) is now burned.
To burn another bank, repeat the procedure from Step 2.
Burn further configuration register banks if desired.
17
When all desired configuration register bank have been burned,
write device OTP Control register 0x00 with OTP_burned bit D7
clear.
Burn OTP Control register clearing OTP_burned bit D7. This
sets the part to load configuration data from OTP on power-up.
18
Exit.
Done.
