REVISION 12/03/15
7
VERSACLOCK
®
6 - 5P49V69xx Family Programmer Board
Programmed Device Testing
As indicated in the Board Overview section, the programmed device can be verified with this same board. To verify, complete the
following:
•
Install R14 (100K
) and then power up to latch the board in hardware selection mode
•
Pull-up or pull-down SEL1 and SEL0 pins to proper levels to match the specific configuration for verification
•
Supply VDDA, VDDD and VDDO0~4
•
Supply a reference signal via CLKIN/CLKINB (needed to populate C20 and C22) or a Crystal (X1) needs to placed, if not
populated in the 3.2x2.5mm package.
•
In order to probe the output(s) of interest the following components need to be placed:
1) R15 and C15 need to be populated to measure OUT0.
2) R17, R18 and J2 to measure OUT1.
3) R20, R21 and J3 to measure OUT1B. R19 s required only when measuring OUT1B and OUT1 in LVDS mode.
4) R26, R27 to measure OUT 2.
5) R30, R31 to measure OUT2B. R29 is only required when measuring OUT2B and OUT2 in LVDS mode.
6) R34, R35 to measure OUT 3.
7) R37, R39 to measure OUT3B. R36 is only required when measuring OUT3 and OUT3B in LVDS mode.
8) R41, R42 to measure OUT4.
9) R44, R45 to measure OUT4B. R43 is only required when measuring OUT4B and OUT4 in LVDS mode.
The recommended values depends on which driver output has been selected – LVDS, LVPECL, HCSL or LVCMOS:
•
LVCMOS requires 33
resistor termination in series.
•
LVDS requires 0
resistor in series and 100
in parallel between the 2 differential outputs.
•
LVPECL requires 0
resistor in series and 180
to ground for each differential signal.
•
HCSL requires 33
resistor in series and 50
to ground for each differential signal.
Please refer to the board schematics on the following pages of this document.
