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©2018 Integrated Device Technology, Inc.
August 30, 2018
VersaClock
®
6E Family Register Descriptions and Programming Guide
To apply the 1.3ns skew on OUT1, write the following values:
Addr – Byte
0x2B – 00
0x2C – 10
0x2F – 74
After writing these values all counters need to be restarted to insert the 1.3ns delay in OUT1 versus the other outputs. The restarting can
be done by toggling the I
2
C global reset in bit 5 of register 0x76. First read register 0x76 to know the setting of all bits. Bit 5 will be “1”
when the outputs are running. Commonly the value of 0x76 will be E3 (hex) and I am assuming this value in the example code below.
The full code to set the 1.3ns skew on the fly will look as follows:
Addr – Byte
0x2B – 00 (OD1_intskew[11:4] = 00, most likely it is already 00; if so, skip this line)
0x2C – 10 (OD1_intskew[3:0] = 1)
0x2F – 74 (OD1_frskew[5:0] = 74)
0x76 – C3 (Set I2C_Global_Reset)
0x76 – E3 (Release I2C_Global_Reset)
Removing the skew again:
0x2B – 00
0x2C – 00
0x2F – 00
0x76 – C3
0x76 – E3
After writing these values on the fly, all counters need to be restarted to insert the 1.3ns delay in OUT1 versus the other outputs.
Output Divider Skew Integer and Fractional Part Registers Settings (
)
The 12 bits integer part of the skew are spread over 2 registers for each output divider and 6 bits are used to configure the fractional part
of the skew.
Table 95. RAM2 – 0x2B: Output Divider 1 Skew Integer Part
Bits
Default Value
Name
Function
D7
0
OD1_intskew[11:4]
12 bits are used to set Output Divider 1 skew integer part in register x2B and x2C.
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
