IDT 5P49V6965, Руководство по описанию регистров и программированию

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31 ©2018 Integrated Device Technology, Inc. August 30, 2018
VersaClock
®
6E Family Register Descriptions and Programming Guide
Output Divider Control Settings ( Table 47 through Table 50 )
These bits are for Output divider's control register settings and are reserved in general. The reset bit for the FOD is active low. The
combination of en_fod (fractional output divider enable bit), sel_ext (the output from previous channel FOD) and selb_norm (the output
from current FOD), will set the divider mode. The integer mode only can be enabled with int_mode bit.
Table 47. RAM2 – 0x21: Output Divider 1 Control Register Settings
Bits Default Value Name Function
D7 1 i2c_resetb1 Reset Fractional Output Divider 1 (FOD1) circuit when set to 0.
D6 0
en_pi_out_cap<2:0> Factory reserved /unused bits. D5 0
D4 0
D3 0 selb_norm1 0000: FOD1 and OUT1 are not used.
00x1: FOD1 uses clock from PLL and OUT1 uses clock from FOD1.
1100: FOD1 disabled and OUT1 uses clock from OUT0. En_refmode needs to be 1.
1111: FOD1 uses clock from OUT0 and OUT1 uses clock from FOD1. En_refmode needs to
be 1.
“int_mode1” sets integer mode for FOD1 (fractional settings will be ignored).
D2 0 sel_ext1
D1 0 int_mode1
D0 1 en_fod1
Table 48. RAM3 – 0x31: Output Divider 2 Control Register Settings
Bits Default Value Name Function
D7 0 i2c_resetb2 Reset Fractional Output Divider 2 (FOD2) circuit when set to 0.
D6 0
en_pi_out_cap<2:0> Factory reserved /unused bits D5 0
D4 0
D3 0 selb_norm2 0000: FOD2 and OUT2 are not used.
00x1: FOD2 uses clock from PLL and OUT2 uses clock from FOD2.
1100: FOD2 disabled and OUT2 uses clock from OUT1. En_aux1 needs to be 1.
1111: FOD2 uses clock from OUT1 and OUT2 uses clock from FOD2. En_aux1 needs to be
1.
“int_mode2” sets integer mode for FOD2 (fractional settings will be ignored).
D2 0 sel_ext2
D1 0 int_mode2
D0 0 en_fod2