IDT 5P49V6965, Руководство по описанию регистров и программированию

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12 ©2018 Integrated Device Technology, Inc. August 30, 2018
VersaClock
®
6E Family Register Descriptions and Programming Guide
Configuration Registers
The internal RAM configuration registers occupy 0x10 to 0x69 ( Table 4 ).
The 4 OTP configuration banks CFG0, CFG1, CFG2, and CFG3 use the same register structure and setting behavior.
The tables with register details refer to the RAM register address for simplicity. Table 23 shows the 3-digit OTP register addresses 0x010
to 0x177 for the four banks of identical configuration registers, and the corresponding RAM register address.
Table 21. RAM0 – 0x0E: Factory Reserved Bits
Bits Default Value Name Function
D7 1
clk3_R_trim[2:0] clk_R_trim: trim for “R” variation, 1LSB is 10%, default is in the middle level. D6 0
D5 1
D4 1
clk4_R_trim[2:0] clk_R_trim: trim for “R” variation, 1LSB is 10%, default is in the middle level. D3 0
D2 1
D1 0 CLK4_amp[0] clk_amp: tune the amplitude of PAD, 1LSB is 10%, default is in the middle level.
D0 0 CLK3_amp[0] clk_amp: tune the amplitude of PAD, 1LSB is 10%, default is in the middle level.
Table 22. RAM0 – 0x0F: Factory Reserved Bits
Bits Default Value Name Function
D7 1 CLK1_amp[2]
clk_amp: tune the amplitude of PAD, 1LSB is 10%, default is in the middle level–Factory
reserved bits.
D6 0 CLK1_amp[1]
D5 0 CLK1_amp[0]
D4 1 CLK2_amp[2]
D3 0 CLK2_amp[1]
D2 0 CLK2_amp[0]
D1 1 CLK3_amp[2]
D0 0 CLK3_amp[1]
Table 23. RAM Configuration Registers and OTP Configuration Registers CFG0, CFG1, CFG2, CFG3
Summary
Register Address
Function
RAM CFG0 CFG1 CFG2 CFG3
0x10 0x010 0x06A 0x0C4 0x11E
Primary Source and Shutdown Register
0x11 0x011 0x06B 0x0C5 0x11F
VCO Band and Factory Reserved Bits
0x12 0x012 0x06C 0x0C6 0x120
Crystal X1 Load Capacitor Register
0x13 0x013 0x06D 0x0C7 0x121
Crystal X2 Load Capacitor Register