Manual Number: 40110-005-2
Page 6
DRAM Memory
The DRAM interface is a 64-bit path that supports up to 256MB of either Fast Page Mode (FPM)
or Extended Data Out (EDO/Hyper Page Mode) memory. All 256MB is cacheable. The
processor board supports 60ns (optimal) or 70ns industry standard 36-bit wide SIMM DRAM
in four 72-pin SIMM sockets. The DRAM speed is selectable via Advanced Chipset Setup which
is described in the Advanced Setup section of this manual.
The SIMM sockets are arranged in two banks. Bank 0 consists of sockets 1 and 2 (U52 & U53);
bank 1 consists of sockets 3 and 4 (U62 & U63).
Note: Two SIMMs of the same memory capacity must be used to fill a memory bank. All SIMMs
must have contacts.
The following SIMMs are supported:
1M x 36, 2M x 36, 4M x 36, 8M x 36, 16M x 36
Memory Hole
The processor board supports a 1MB memory hole option at 512KB-640KB or 15MB-16MB.
Error Checking and Correction/Parity
The memory interface includes parity checking and supports ECC mode (via BIOS setting) for
single-error correction, double-error detection and detection of all errors confined to a single
nibble.
Note: ECC is implemented using the eight parity bits available on the two SIMM modules in a
bank. FPM or EDO parity SIMMs must be used for ECC to operate properly.
PCI Local Bus Interface
The processor board is fully compliant with the PCI Local Bus 2.1 Specification. It has optimized
the PCI interface to allow the CPU to sustain the highest possible bandwidth (greater than
100MB/sec sustained) and low latency of the PCI Bus. It supports four PCI masters, pipelined
snoop ahead feature and improved PCI to DRAM write-back policy. The PCI Local Bus
interfaces to the on-board PCI Ultra SCSI controller, the optional Cirrus SVGA controller and
to standard PCI option cards in the backplane. The PCI Local Bus interface to the backplane is
compliant with the PCI Industrial Computer Manufacturers Group (PICMG) 2.0 Specification.
PCI Super VGA Interface (Optional)
The Cirrus Logic GD5446 video interface is a PCI Local Bus device which supports pixel
resolutions up to 1280 x 1024 non-interlaced and 16.8 million colors at resolutions up to 1024
x 768. The processor board provides up to 2MB of on-board EDO display memory with a 64-
bit wide data path and 80MHz memory clock. It displays in full-screen, full-motion up to 30
frames per second, true color at 1024 x 768. Independent graphics and video streams can be
displayed on-screen with true-color video and 256-color graphics. Software drivers for
enhanced performance and resolution are available for the most popular operating systems.
Содержание SB686P Series
Страница 2: ...Page ii...
Страница 14: ...Manual Number 40110 005 2 Page 4...
Страница 27: ...Manual Number 40110 005 2 Page 17 ISA Bus Pin Numbering...
Страница 37: ...Manual Number 40110 005 2 Page 27 PCI Local Bus Pin Numbering...
Страница 56: ...Manual Number 40110 005 2 Page 46 This page intentionally left blank...
Страница 80: ...Manual Number 40110 005 2 Page 70 This page intentionally left blank...
Страница 122: ......
Страница 124: ......
Страница 126: ......