ICP Electronics ROCKY-3732EVS, Руководство пользователя

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DRAM Timing By SPD
This item allows you to select the value in this field, depending on whether the
board has paged DRAMs or EDO (extended data output) DRAMs.
The Choice:
Enabled, Disabled.
DRAM Clock
This item allows you to control the DRAM speed.
The Choice: Host Clock, HCLK-33M.
SDRAM Cycle Length
When synchronous DRAM is installed, the number of clock cycles of CAS
latency depends on the DRAM timing. Do not reset this field from the default
value specified by the system designer.
The Choice: 2, 3.
Memory Hole
In order to improve performance, certain space in memory is reserved for ISA
cards. This memory must be mapped into the memory space below 16MB.
The Choice: 15M-16M, Disabled.
P2c/C2P Concurrency
This item allows you to enable/disable the PCI to CPU, CPU to PCI
concurrency.
The choice: Enabled, Disabled.
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-
FFFFFh, resulting in better system performance. However, if any program
writes to this memory area, a system error may result.
The Choice: Enabled, Disabled.
OnChip USB
This should be enabled if your system has a USB installed on the system
board and you want to use it. Even when so equipped, if you add a higher
performance controller, you will need to disable this feature.
The Choice: Enabled, Disabled.