ICP Electronics ROCKY-3732EVS, Руководство пользователя

Страница: 38 / 64

38
4.7 Advanced Chipset Features
CMOS Setup Utility – Copyright © 1984 – 2000 Award Software
Advanced Chipset Features
DRAM Timing By SPD [Enabled]
DRAM Clock [Host CLK]
SDRAM Cycle Length [3]
Bank Interleave [Disabled]
Memory Hole [Disabled]
P2C/C2P Concurrency [Enabled]
System BIOS Cacheable [Disabled]
OnChip USB [Disabled]
USB Keyboard Support [Disabled]
USB Mouse Support [Disabled]
OnChip Sound [Auto]
CPU to PCI Write Buffer [Enabled]
PCI Dynamic Bursting [Enabled]
PCI Master 0 WS Write [Enabled]
PCI Delay transaction [Enabled]
PCI#2 Access #1 Retry [Enabled]
PCI Latency Timer(Clock) [64]
Memory Parity/ECC Check [Disabled] Item Help
_______________________
Menu Level
Ø
↑↓←→
Move Enter: Select +/-/PU/PD: Value F10:Save ESC: Exit F1:General Help
F5:Previous Values F6:Fail-safe defaults F7:Optimized Defaults
This section allows you to configure the system based on the specific features
of the installed chipset. This chipset manages bus speeds and access to
system memory resources, such as DRAM and the external cache. It also
coordinates communications between the conventional ISA bus and the PCI
bus. It must be stated that these items should never need to be altered. The
default settings have been chosen because they provide the best operating
conditions for your system. The only time you might consider making any
changes would be if you discovered that data was being lost while using your
system.
DRAM Settings
The first chipset settings deal with CPU access to dynamic random
access memory (DRAM). The default timings have been carefully
chosen and should only be altered if data is being lost. Such a
scenario might well occur if your system had mixed speed DRAM chips
installed so that greater delays may be required to preserve the
integrity of the data held in the slower memory chips.