ICP CON I-7188XC Series, Руководство пользователя

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Address bus (output): A0 ~ A6
Data Bus (tri-state, bi-direction): D0 ~ D7
/CS, /RD and /WR: These 3 signals will be synchronous to
CLOCKA (Pin3 of JP1) and asynchronous to ARDY (Pin4 of JP1)
The /CS will be active if the program needs to input/output data
from I/O address 0 to 0xff.
Note: The Pin15 and Pin17of JP2 are reserved by I-7188XC(D), user
must leave these two pins N/C. For more detailed information, refer to
“
I/O Expansion Bus for 7188X/7188E User’s Manual ”.
4.12.2 Reconfiguring the I-7188XC(D)
There are three DO channels and two DI channels from the pin-4 to
pin-8 of the I-7188XC(D). For the application of “Customized 7000
Modules”, these 5 pins can be hardware reconfigured to other functions
as follows:
Step 1: Remove the reconfiguration-resistor as follows:
If DO3 is reconfigured, remove R19
If DO2 is reconfigured, remove R20
If DO1 is reconfigured, remove R21
If DI3 is reconfigured, remove R22
If DI2 is reconfigured, remove R23
Then, the onboard DI/DO functions can be disabled.
Step 2: Install a 5-pin male reconfiguration-jumper into the TP0 of the
I-7188XC(D)
Step 3: Design a 5-pin female reconfiguration-jumper in an expansion
board for connection to TP1. Then the external signals from
pin-4 to pin-8 can be connected to an expansion board. The
user can refigure these 5 D/I/O pins to their special
requirements now.
Note:
If the DO2 is reconfigured to DI, its initial state must be High. If its
initial state is Low, system clock will be reduced to 10M. So all
clock-related libraries would only be at half-speed.
I-7188XC Series User’s Manual(Ver.1.0, Apr/2007,7MH-21-10) ---
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