IM242S
User Manual
11
3. Theory of Operation
3.1 Overview
Figure 2 shows the operation of ICOP IM242S from the system level, including the major hardware
blocks.
Figure 4: ICOP IM242S Block Diagram
ICOP IM242S integrates a SATA III controller and NAND flash memories. Communication with the
host occurs through the host interface, using the standard ATA protocol. Communication with the
flash device(s) occurs through the flash interface.
3.2 SATA III Controller
ICOP IM242S is designed with
88NV1120
, a SATA III 6.0Gbps (Gen. 3) controller. The Serial ATA
physical, link and transport layers are compliant with Serial ATA Gen 1, Gen 2 and Gen 3
specification (Gen 3 supports 1.5Gbps/3.0Gbps/6.0Gbps data rate). The controller has 2 channels
for flash interface.
3.3 Error Detection and Correction
ICOP 2.5”SATA SSD 3ME4 is designed with hardware LDPC ECC engine with hard-decision and
soft-decision decoding. Low-density parity-check (LDPC) codes have excellent error correcting