C - 3 - 3
The portion of the signal is applied to the PLL section as the
comparison signal. The PLL section compares the phase of
divided VCO frequency to the reference frequency (X204;
25 MHz). The output signal from the PLL section (IC404, pin
30) is passed through the loop filter and is then applied to
the RX 2nd VCO circuit.
3-3-3 RX 3RD PLL CIRCUIT (IF UNIT)
The RX 3rd PLL circuit oscillates the RX 3rd LO frequency
and the signal is applied to the 3rd mixer section in the I/Q
demodulator IC (IC401).
The oscillated signal from the RX 3rd VCO circuit (Q401,
Q402, D401) is amplifi ed at the buffer amplifi er (Q403) and
then applied to the 3rd mixer section of the I/Q demodulator
IC (IC401, pin 26).
The portion of the signal is applied to the PLL section as the
comparison signal. The PLL section compares the phase of
divided VCO frequency to the reference frequency (X204;
25 MHz). The output signal from the PLL section (IC401, pin
22) is passed through the loop filter and is then applied to
the RX 3rd VCO circuit.
3-3-4 TX 3RD PLL CIRCUIT (IF UNIT)
The 3rd PLL circuit oscillates the TX 3rd LO frequency
and the signal is applied to the 3rd mixer section in the I/Q
modulator (IC201).
The oscillated signal from the TX 3rd VCO circuit (Q201,
Q202, D201) is applied to the tripler circuit (Q203) and then
applied to the 3rd mixer section of the I/Q modulator (IC201,
pin 26).
3-4 POWER SUPPLY CIRCUITS
Line
Description
5 V
Common 5 V controlled by the +5 V regulator
circuit (IC1). The output voltage is applied to
the baseband clock circuit (Q1, X1), etc.
3.3 V
Common 3.3 V converted from the 5V line
by the 3.3 V regulator circuit (IC12). The output
voltage is applied to the FPGA IC (IC11) and
A/D converter (IC9), etc.
2.5 V
Common 2.5 V converted from the 5V line
by the 2.5 V regulator circuit (IC13). The output
voltage is applied to the FPGA IC (IC11), etc.
IC204
IC404
IC401
PLL
TX 2nd
VCO
LOOP
×2
BPF
FI202
FI402
686.75
MHz
1st IF signal from
the 10 GHz module
1st IF signal to
the 10 GHz module
748
MHz
I/Q signals from
FPGA
circuit
I/Q signals to
FPGA
circuit
350.5
MHz
X204
25
MHz
602.25
MHz
IC201
PLL
TX 3rd
VCO
LOOP
×3
PLL
RX 2nd
VCO
LOOP
×2
BPF
PLL
RX 3rd
VCO
LOOP
CPU
IC509
The portion of the signal is applied to the PLL section as the
comparison signal. The PLL section compares the phase of
divided VCO frequency to the reference frequency (X204;
25 MHz). The output signal from the PLL section (IC201, pin
22) is passed through the loop filter and is then applied to
the TX 3rd VCO circuit.
3-3-5 TX 2ND PLL CIRCUIT (IF UNIT)
The 2nd PLL circuit oscillates the TX 2nd LO frequency
and the signal is applied to the 2nd mixer section in the IF
converter (IC204).
The oscillated signal from the TX 2nd VCO circuit (Q204,
Q205, D204) is applied to the tripler circuit (Q206) and then
applied to the 2nd mixer section of IF converter (IC204, pin
40).
The portion of the signal is applied to the PLL section as the
comparison signal. The PLL section compares the phase of
divided VCO frequency to the reference frequency (X204;
25 MHz). The output signal from the PLL section (IC204, pin
30) is passed through the loop filter and is then applied to
the TX 2nd VCO circuit.
• PLL CIRCUITS