4 - 3
4-3 PLL CIRCUITS
4-3-1 GENERAL (MAIN UNIT)
The PLL circuit provides stable oscillation of the transmit
frequency and receive 1st LO frequency. The PLL circuit
compares the phase of the divided VCO frequency to
the reference frequency. The PLL output frequency is
controlled by a crystal oscillator and the divided ratio of the
programmable divider.
IC8 on the MAIN unit is a dual PLL IC which controls both
VCO circuits for Tx and Rx, and contains a prescaler,
programmable counter, programmable divider, phase
detector, charge pump, etc.
The PLL circuit , using a one chip PLL IC (MAIN unit; IC8),
directly generates the transmit frequency and receive 1st IF
frequency with VCO. The PLL sets the divided ratio based
on serial data from the CPU on the LOGIC BOARD and
compares the phases of VCO signals with the reference
oscillator frequency. The PLL IC detects the out-of-step
phase and output from pins 8 for Tx and Rx. The reference
frequency (21.25 MHz) is oscillated at X2 (MAIN unit).
4-3-2 TX AND RX LOOP (MAIN UNIT)
The generated signal at the VCO (Q13, Q14, D11–
D14) enters the PLL IC (IC8, pin 2) and is divided at the
programmable divider section and is then applied to the
phase detector section.
The phase detector compares the input signal with a
reference frequency, and then outputs the out-of-phase
signal (pulse-type signal) from pin 8.
The pulse-type signal is converted into DC voltage (lock
voltage) at the loop filter (R211–R213, C252, C254), and is
then applied to varactor diodes (D13, D14) of the VCO to
stabilize the oscillated frequency.
4-3-4 VCO CIRCUIT (MAIN UNIT)
The VCO outputs from Q13, Q14 are buffer-amplified at
the buffer amplifiers (Q15 and Q16), and are then sent to
the Tx/Rx switch (D16 and D17). The receive LO signal is
applied to the 1st mixer circuit (Q2) through a low-pass filter,
and the transmit signal is applied to the YGR amplifier (Q17).
A portion of the VCO output is reapplied to the PLL IC (IC8,
pin 2) via the buffer amplifier (Q26).
4-2-5 APC CIRCUIT (MAIN UNIT)
The APC circuit stabilizes transmit output power.
The RF output signal from the power amplifier (IC4) is
detected at the power detector circuit (D21, D22, L31) and
is then applied to one of the differential amplifier inputs (Q21,
pin 3) via the High/Low control circuit (Q22, R137). The
hift register
Prescaler
Phase
detector
Loop
filter
Programmable
counter
Programmable
divider
X2
21.25 MHz
21.25 MHz signal to the
FM IF IC (IC1, pin 2)
VCO
Buffer
Buffer
Buffer
Q16
Q26
Q15
3
4
5
P TB
IC (PLL IC)
PC
PDATA
to transmitter circuit
to 1st mixer circuit
D17
D16
17
16
8
2
Q13, Q14, D11 D14
T5
D21
D22
L31
TMUT signal from the CPU
(LOGIC board; IC1, pin 51)
HV
5V
1
2
3
4
H/L
TXD T signal to the CPU
(LOGIC board; IC1, pin 2)
Q23
Q21
Q2
Q22
C177
R13
R138
Q18
YGR
amp.
RF signal
from PLL
to the antenna
RF detector
circuit
APC control circuit
Power module
IC4
R133
R136
R135
applied voltage controls the differential amplifier output (Q21,
pin 1) and the bias voltage control (Q23). Thus the APC
circuit maintains a constant output power.
• APC CIRCUIT
• PLL CIRCUITS