4 - 5
4-7 CPU PORT ALLOCATIONS
Pin
NO.
Port name
Description
2
KEYM
Input port for keys on HM-150B/SW.
Approx. 2.02 V: [
Y
] key is pushed.
Approx. 3.00 V: [
Z
] key is pushed.
Approx. 3.84 V: [H/L] key is pushed.
3
TXDET
Input port for transmit detected voltage.
4
LBAT
Input port for low battery detecting.
5
SQL
Input port for "NOISE" signal from the squelch
amplifi er (IC11, pin 4).
6
SQLV
Input port for squelch adjustment pot (SQL
BOARD; R1).
7
WXDEC
Input port for weather alert signal from the
LPF (Q38).
8
PDATA
Outputs data signal to the PLL IC (IC1, pin 5).
9
PCK
Outputs clock signal to the PLL IC (IC1, pin 4).
10
PSTB
Outputs strobe signal to the PLL IC (IC1, pin3).
12
EVDATA
Outputs volume control signal to the volume
ccontroller (IC13, pin 5) for PA circuit.
13
EVCK
Outputs clock signal to the volume ccontroller
(IC13, pin 4) for PA circuit.
14
DSDEC
Input port for the DSC decode signal from the
DSC decoder (IC15, pin 7).
28,
29
CONT1,
CONT0
Output LCD contrast adjust signal to the CPU
(IC1, pin 134).
32
COMTXD
Outputs serial data signal to the connected
HM-157 (Optional product).
33
COMRXD
Input port for the serial data signal from the
connected HM-157 (Optional product).
34
ECK
Outputs clock signal to the EEPROM (LOGIC
BOARD; IC4, pin 6).
35
EDATA
I/O port for the EEPROM (LOGIC BOARD;
IC4, pin 5) control data.
37
NMTXD
Outputs NMEA command signal.
38
NMRXD
Input port for the NMEA signal.
48
PWR
Input port for power switch (VR BOARD; R1).
Low: When [VOL] is pushed.
49
PAMUTE
Outputs control signal to the AF (Public Ad-
dress) mute circuit (Q65).
High: During mute.
50
PWRON
Outputs power control signal to the power
control circuit (Q61, Q62).
High: While the transceiver is switched ON.
51
TMUTE
Outputs transmit mute signal to the APC circuit
(IC12, pin 3).
High: During mute.
53
RCV
Outputs control signal to the R5 control circuit
(Q53, Q54).
High:
While
receiving.
54
H/L
Outputs TX power control signal to the TX
power control circuit (Q17, D11).
High:
25
W
Low:
1
W
55
ATT
Outputs attenuator control signal to the
attenuator (D22).
High: Attenuator ON.
57
PTT
Input port for the [PTT] switch (HM-150B/SW; S1).
Low: [PTT] key is pushed.
60
UNLK
Input port for the "UNLK" signal from the PLL
IC (IC1, pin7).
High: PLL circuit is unlocked.
Pin
NO.
Port name
Description
61
DTRS
Input port for the [DISTRESS] key (LOGIC
BOARD; S9).
Low: [DISTRESS] key is pushed.
62
RMUTEP
Outputs AF (Public Address) mute signal to
the AF mute circuit (IC4, pin12).
Low: During mute.
63
RMUTES
Outputs AF mute signal to the AF mute circuit
(IC4, pin 5) for the connected HM-157 (Op-
tional product).
Low: During mute.
64
RMUTEM
Outputs AF (internal speaker) mute signal to the
AF mute circuit (IC4, pin 6).
Low: During mute.
65
MMUTEP
Outputs microphone (Public Address) mute
signal to the AF mute circuit (IC5, pin 6).
Low: During mute.
66
MMUTES
Outputs microphone mute signal to the AF
mute circuit (IC5, pin 5) for the connected
HM-157 (Optional product).
Low: During mute.
67
MMUTEM
Outputs microphone (HM-150B/SW) mute sig-
nal to the AF mute circuit (IC5, pin 13).
Low: During mute.
68
PTTS
Outputs AF/MIC control signal to the AF mute
circuit (IC6, pin 5).
High: PTT switch (HM-157) is pushed
69
PTTM
Outputs AF/MIC control signal to the AF mute
circuit (IC5, pin 12).
70
LO/DX
Input por t for the [LO/DX] key (LOGIC
BOARD; S8).
Low: [LO/DX] key is pushed.
71
DSC
Input port for the [DSC] key (LOGIC BOARD; S7).
Low: [DSC] key is pushed.
72
PA
Input port for the [PA] key (LOGIC BOARD; S6).
Low: [PA] key is pushed.
73
CH/WX
Input por t for the [CH/WX] key (LOGIC
BOARD; S5).
Low: [CH/WX] key is pushed.
74
SCAN
Input port for the [SCAN] key (LOGIC BOARD; S4).
Low: [SCAN] key is pushed.
75
CH16
Input port for the [16] key (LOGIC BOARD; S3).
Low: [16] key is pushed.
76
DOWN
Input port for the [
Z
] key (LOGIC BOARD; S2).
Low:
[
Z
] key is pushed.
77
UP
Input port for the [
Y
] key (LOGIC BOARD; S1).
Low:
[
Y
] key is pushed.
138
DIM
Outputs dimmer control signal to the LCD control
circuit (LOGIC BOARD; Q2, Q3).
139
BEEP
Outputs beep signal to the AF amplifi er (IC9, pin 1).
141
DS/BPF
• While transmitting:
Outputs DSC encode signal as "DSENC"
to the LPF (IC8, pin 5) via the buffer amplifi er
(LOGIC BOARD; IC5, pins 1, 3).
• While receiving:
Outputs tuning signal as "BPFV" to the
tunable BPFs (D25–D28) via buffer amplifi er
(LOGIC BOARD; IC5, pins 5, 7).
