iC-Haus iC-PV EVAL PV1M1, Руководство пользователя

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prel
imin
ary
prel
imin
ary iC-PV EVAL PV1M1
EVALUATION KIT DESCRIPTION
Rev A6, Page 5/9
CIRCUIT SCHEMATIC
B
B
B
B
B B
B B
HALL SENSOR
PCOS
NSIN
CONTROL
AMPLITUDE
RAM
D
SIN
iC-MHM
LINE
DRIVER
BiSS
INTERFACE
EEPROM
iC-PV
HALL FRONTEND
SUPPLY SWITCH
OSCILLATOR
D
over JP1 on PV1M1
SIN
I2C MULTI MASTER
ERROR
MONITOR
MULTITURN COUNTER
SERIAL INTERFACE
MT-INTERFACE
ERROR
optional preset line
MULTI MASTER
MONITOR
I2C
DIGITAL-IO
PSIN
NCOS
NERR
VDDS
PRE
DI_P1
VDDS
VDD
DO_P0
VDD VBAT
SEL
GNDA
P1
SCL
NERR
VDD
MCL
MDI
GND
SCL
SDA
P3
P2
NSIN
GNDS
MAO
SLO
NCOS
PSIN
PCOS
SDA
CLK_N1
SDA
SCL
MA
SLI
GND
100nF
1μF 100nF
MAO
MA
SLI
SLO
VDD
GND
1μF
100nF
100nF
Figure 12: Circuit principle. Connection of iC-MHM pin P3 to iC-PV pin PRE using JP1 is optional.
onlu For capacitors
VBAT
PMEG2005
VDDS
. -T
1 C"I 1
c
A
_ _ 01
1
'1
R2
VDD
C3 1 c2_1_
550 c7 1 U3-S
100nFzr 10uFzr
J2-VEl__
3
'1
OMR_B3S_100
�
0
tr­
S#
S1
1 2
U2
i C-PV
PV _ VDDS 1 71 VDDS
C8--1L
100nF
�
2
8
VDD
LOGIC
SIN/DIG CONVERTER
��
i
1
��I
SUB GNDA
IEPAD
15
2
100nF
I
2
'1
LC15B
_L _L
1
A
GND
�JZ�B
_f
NCS
JP2
NCS_EXT
J2-NC
C
U1
2 10
NERRI 3
i
SDA
H
SCL 15
1
J1
r
1 ���1
111
1
so·
SL:L
_i__Jj
iC-MHM
17
VDDS
VDD 2
'1
VP _IN
J2-VDD
- - -·TP"l-1
1 �·
1
TP"l-2
2
- - �•-iP5-1
- - -•-1P5-2
- -
--•iP5-1
- - �•-1P5-2
J2-MA
--3
J2-NMA
- - 5
�
MA 1
MA
NMA 2 NMA
SLI 21 SLI
J2-SLI
- - 8
EPAD 115
NSLI 20 NSLI 12 J2-NSLI
SLO 23 SLO
NSLO 22 NSLO I
GNDI 25
GND_ IN
J2-SL
- -
'1
J2-NSL
- - 5
J2-GND
2
PROJECT BLOCK REV T ITLE
PV1M O 1 DEMONSTRATOR
DESIGN$pcb_pv1M_0/design/pv1M1/net/pv1M_1_0/pcb_design_vpt
SHEET # VER DATE EDIT VIS Haus
sheetl 1/1 30 27.03.201'1 HN PCB
Figure 13: Circuit diagram. Do not install diode D1 for use with battery.