Configur ation
117
Bit 1
Other
Bit 2
Unknown
Bit 3
Fast-paged
Bit 4
Static
column
Bit 5
Pseudo-static
Bit 6
RAMBUS
Bit 7
Synchronous
Bit 8
CMOS
Bit 9
EDO
Bit 10
Window
DRAM
Bit 11
Cache
DRAM
Bit 12
Non-volatile
Bits 13:15
Reserved, set to 0
Interpretation of SEL format for PCI bus related errors:
The following table defines
the data byte formats for PCI bus-related errors logged by the BIOS.
Field
IPMI definition
BIOS-specific implementation
Generator ID
7:1
System software ID or IPMB slave
address. 1=ID is system software
ID; 0=ID is IPMB slave address.
7:4
0x3 for system BIOS
3:1
0 Format rev ision. Revision of the data format for
OEM data bytes 2 and 3. For this revision of the
specification, set this field to 0. All other rev isions are
reserved for now.
0
1 = ID is system software ID.
As a result, the generator ID byte will start from 0x31 and
go up to 0x3f, in increments of 2 for events logged by the
BIOS.
EvMRev
Event Message Revision
This field is used to identify different revisions of the
Event Message format. The rev ision number shall be 03h
for Event Messages that comply with the format given in
this specification.
Sensor Type
0x13 for critical interrupt.
Sensor Number
Number of sensor that generated this
event
Unique value for each type of ev ent because IPMI
specification requires as such. This field has no other
significance. Should not be displayed to the end-user if
the event is logged by BIOS.
Event Direct /
Event Type
0x6F if event offsets are specific to the
sensor
7
0= Assertion Event, 1 = Deassertion Event
6:0
0x6F
Event Data 1
7:6
00 = unspecified byte 2; 10 = OEM
code in byte 2.
5:4
00 = unspecified byte 3; 10 = OEM
code in byte 3. (BIOS will not use
encodings 01 and 11 for errors
covered by this document.).
3:0...
Offset from Event Trigger for
discrete event state.
Follow IPMI definition. If either of the two data bytes
following this do not have any data, that byte should be
set to 0xff, and the appropriate field in event data 1 should
indicate that it is unspecified.
3:0 is 04 for PCI PERR and 05 for PCI SERR.
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