12.5 Data Register
This register is used to transfer data blocks between the device data buffer and the host. It is also the
register through which sector information is transferred on a Format Track command and configuration
information is transferred on an Identify Device command.
All data transfers are 16 bits wide, except for ECC byte transfers, which are 8 bits wide. Data transfers
are PIO only.
The register contains valid data only when DRQ=1 in the Status Register.
12.6 Device Control Register
0
–IEN
SRST
1
–
–
–
–
0
1
2
3
4
5
6
7
Device Control Register
Figure 60. Device Control Register
Bit Definitions
SRST (RST) Software Reset. The device is held reset when RST=1. Setting RST=0 re-enables the
device.
The host must set RST=1 and wait for at least 5 us before setting RST=0 to ensure that
the device recognizes the reset.
-IEN
Interrupt Enable. When -IEN=0 and the device is selected, device interrupts to the host
will be enabled. When -IEN=1 or the device is not selected, device interrupts to the host
will be disabled.
12.7 Drive Address Register
–DS0
–DS1
–H0
–H1
–H2
–H3
–WTG
HIZ
0
1
2
3
4
5
6
7
Drive Address Register
Figure 61. Drive Address Register
This register contains the inverted drive select and head select addresses of the currently selected drive.
Bit Definitions
HIZ
High Impedance. This bit is not driven and will always be in a high impedance state.
-WTG
-Write Gate. This bit is 0 when writing to the disk device is in progress.
-H3,-H2,-H1,-H0-
-Head Select. These four bits are the one's complement of the binary coded address of
the currently selected head. -H0 is the least significant.
Deskstar 60 GXP Hard disk drive specification
69
Содержание IC35L020 - Deskstar 20 GB Hard Drive
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