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9.1.5 PIO timings
The PIO cycle timings meet Mode 4 of the ATA/ATAPI-5 description.
IOCS16-(*)
t1
t9
t0
t2
t2i
t3
t4
t5
t6
t8(*)
t7(*)
t1
tA
tB
Read data
DD00-DD15
DIOR-,
DIOW-
CS0-,CS1-
DA0-2
Write data
DD00-DD15
IORDY
1250
–
IORDY pulse width
tB
35
–
IORDY setup time
tA
-
10
DIOR-, DIOW- to CS0-, CS1-, DA0-2 valid hold
t9
30
–
CS0-, CS1-, DA0–02 invalid to IOCS16- negation
t8(*)
40
–
CS0-, CS1-, DA0–02 valid to IOCS16- assertion
t7(*)
–
5
DIOR- data hold
t6
–
20
DIOR- data setup
t5
–
10
DIOW- data hold
t4
–
20
DIOW- data setup
t3
–
25
DIOR-, DIOW- recovery time
t2i
–
70
DIOR-, DIOW- pulse width
t2
–
25
CS0- CS1-, DA00–02 valid to DIOR-, DIOW- setup
t1
–
120
Cycle time
t0
Maximum
(ns)
Minimum
(ns)
Parameter descriptions
(*) Up to ATA-2 (modes—0, 1, and 2)
Figure 25. PIO cycle time
9.1.5.1 Write DRQ interval time
For write sectors and write multiple operations, 3.8 us is inserted from the end of negation of the DRQ bit
until the setting of the next DRQ bit.
9.1.5.2 Read DRQ interval time
For read sectors and read multiple operations the interval from the end of negation of the DRQ bit until
the setting of the next DRQ bit is as follows:
y
If a host reads the status register only before the sector or block transfer, the DRQ interval is 4.2 us.
If a host reads the status register after or both before and after the sector or block transfer, the DRQ
interval is 11.5 us.
Deskstar 60 GXP Hard disk drive specification
30
Содержание IC35L020 - Deskstar 20 GB Hard Drive
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