9.0
Registers
Invalid address
x
x
x
A
A
Command
Status
1
1
1
N
A
2 LBA bits 24–27
1
LBA bits 24–27
1
0
1
1
N
A
Device/Head
Device/Head.
0
1
1
N
A
2 LBA bits 16–23
1
LBA bits 16–23
1
1
0
1
N
A
Cylinder High
Cylinder High
1
0
1
N
A
2 LBA bits 8–15
1
LBA bits 8–15
1
0
0
1
N
A
Cylinder Low
Cylinder Low
0
0
1
N
A
2 LBA bits 0–7
1
LBA bits 0–7
1
1
1
0
N
A
Sector Number
Sector Number
1
1
0
N
A
Sector Count
Sector Count
0
1
0
N
A
Features
Error Register
1
0
0
N
A
Data
Data
0
0
0
N
A
Command block registers
Not used
Device Address
1
1
1
A
N
Device Control
Alternate Status
0
1
1
A
N
Not used
Data bus high impedance
x
0
1
A
N
Not used
Data bus high impedance
x
x
0
A
N
Control block registers
Not used
Data bus high impedance
x
x
x
N
N
WRITE (DIOW–)
READ (DIOR–)
DA0
DA1
DA2
CS1–
CS0–
Functions
Addresses
1
Mapping of registers in LBA mode
X = may be A or N
N = signal negated
A = signal asserted
Logic conventions:
Figure 66. Register Set
Communication to or from the device is through an I/ O Register that routes the input or output data to or
from registers addressed by the signals from the host (CS0
–
, CS1
–
, DA2, DA1, DA0, DIOR
–
and
DIOW
–
).
The Command Block Registers are used for sending commands to the device or posting status from the
device.
The Control Block Registers are used for device control and to post alternate status.
Deskstar 40GV & 75GXP hard disk drive specifications
69
Содержание DTLA-305040 - Deskstar 41.1 GB Hard Drive
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