IAI SW-4000M-PMCL, Руководство пользователя

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SW-4000M-PMCL
B
Trigger
EEN
LVAL
■ When [ExposureMode] is [TriggerWidth]
• Line Start Trigger : On
PWC mode
//
A
C
D
F
//
DVAL
//
//
E
*) About CL Pixel Clock [MHz] and time of 1Clock
CL Pixel Clock [MHz] : 31.70 1CLK : 0.0315μs
CL Pixel Clock [MHz] : 42.41 1CLK : 0.0236μs
CL Pixel Clock [MHz] : 63.39 1CLK : 0.0158μs
CL Pixel Clock [MHz] : 84.82 1CLK : 0.0118μs
TapGeometry Bit/Pixel
CL Pixel
Clock[MHz]
Line Period
(CLK) [A]
Delay Time
from Trigger
rising to EEN
rising (μs)
[B]
Delay time
From Trigger
falling to EEN
falling (μs)
[C]
Period from
EEN Falling
to LVAL
rising (μs)
[D]
Data
invalid time
(CLK) [E]
Data
valid time
(CLK) [F]
31.70 2058 1.6 1.2 17.9 10 2048
42.41 2065 1.6 1.2 17.8 17 2048
63.39 2058 1.6 1.2 17.8 10 2048
84.82 2066 1.6 1.2 17.8 18 2048
31.70 1371 1.6 1.2 17.9 7 1364
42.41 1376 1.6 1.2 17.8 12 1364
63.39 1372 1.6 1.2 17.8 8 1364
84.82 1376 1.6 1.2 17.8 12 1364
31.70 1029 1.6 1.2 17.9 5 1024
42.41 1033 1.6 1.2 17.8 9 1024
63.39 1030 1.6 1.2 17.8 6 1024
84.82 1034 1.6 1.2 17.8 10 1024
31.70 515 1.6 1.2 17.9 3 512
42.41 517 1.6 1.2 17.8 5 512
63.39 516 1.6 1.2 17.8 4 512
84.82 518 1.6 1.2 17.8 6 512
31.70 412 1.6 1.2 17.9 3 409
42.41 413 1.6 1.2 17.8 4 409
63.39 412 1.6 1.2 17.8 3 409
84.82 425 1.6 1.2 17.8 16 409
1X8 8/10
1X10 8
1X2 8/10
1X3 8
1X4 8/10
• Common to [Binning Off] and [Vertical Binning On]