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2.2.

7、DVI Digital Receiver SiI161B

General：

The Si

l

161B receiver uses Panel Link Digital technology to support high-resolution

displays up to UXGA. The Si

l

161B receiver supports up to true color panels (24 bit/pixel,

16.7M colors) in 1 or 2 pixels/clock mode. In addition, the receiver data output is time
staggered to reduce ground bounce that affects EMI. All Panel Link products are
designed on a scaleable CMOS architecture. This ensures support for future
performance requirements while maintaining the same logical interface. With this
scalable architecture, system designers can be assured that the interface will be fixed
through a number of technology and performance generations.

Pin Function Descriptions

：

Pin(s) Name

Function

90 RX0+

TMDS Low Voltage Differential Signal input data pairs

91 RX0-

TMDS Low Voltage Differential Signal input data pairs

85 RX1+

TMDS Low Voltage Differential Signal input data pairs

86 RX1-

TMDS Low Voltage Differential Signal input data pairs

80 RX2+

TMDS Low Voltage Differential Signal input data pairs

81 RX2-

TMDS Low Voltage Differential Signal input data pairs

93 RXC+

TMDS Low Voltage Differential Signal input clock pair.

94 RXC-

TMDS Low Voltage Differential Signal input clock pair.

49～56

QO0～QO7

8bit odd-pixel Blue output

59～66

QO8～QO15

8bit even-pixel Green output

69～75,77

QO16～QO23

8bit odd-pixel Red output

10～17

QE0～QE7

8bit even -pixel Blue output

20～27

QE8～QE15

8bit even -pixel Green output

30～37

QE16～QE23

8bit even -pixel Red output

99 RESERVED

Must be tied HIGH for normal operation.

100 OCK_INV

ODCK Polarity. A LOW level selects normal ODCK
output. A HIGH level selects inverted ODCK output.

1 HS_DJTR

This pin enables/disable the HSYNC dejitter function.
To enable the HSYNC function this pin should be tied
high. To

2 PD

Power Down (active LOW). A HIGH level indicates
normal operation. A LOW level indicates power down
mode.

3 ST

Output Drive. A HIGH level selects HIGH output drive
strength. A LOW level selects LOW output drive
strength.

4 PIXS

Pixel Select. A LOW level indicates one pixel (up to
24-bits) per clock mode using QE[23:0]. A HIGH level
indicates two pixels (up to 48-bits) per clock mode
using QE [23:0] for first pixel and QO[23:0] for second
pixel.

7 STAG_OUT

Staggered Output. A HIGH level selects normal
simultaneous outputs on all odd and even data lines.

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Содержание H-PDP4201

Страница 1: ...PDP TELEVISION SERVICE MANUAL MODEL NO H PDP4201 Hyundai Please read this manual carefully before service 1 ...

Страница 2: ...res and Circuit PartⅡ Introduction on Circuit Functions of PT4206 PartⅢ Analysis on Signal Process of PT4206 PartⅣ Typical Defectives and Repair of PT4206 Annex 1 Main Assembly DrawingⅠ Ⅱ of PT4206 2 Wire Connecting Drawing of PT4206 2 ...

Страница 3: ...e PDP Panel Resolution 852 3 RGB 480 Colors 16 777 216 Dot Pitch 1 095mm H 1 110mm V Brightness High brightness Contrast High contrast Lifespan of Panel 20000 Hours Viewing Angle U D 160 L R 160 Response Time 933mm H 533mm V Remarks Brightness and contrast may vary because of different panels being used PT4206 mainly uses SAMSUNG SDI panel model S42SD YD04 or S42SD YD05 注 1 1 2 Specification Sheet...

Страница 4: ...n Yes Output Voltage 2 5W Audio Effect WOW NICAM IGR Yes Video YpbPr Audio Input Audio L R Audio PC DVI Audio Input Audio L R Input Voltage 220V 50Hz Rating Consumption 400W Standby Consumption 3W 1 2 Main Features 1 2 1 Terminals RF Input 1 Rear S Terminal Input 1 Rear A V Input RCA 1 Rear YCbCr RCA 1 Rear DTV YPbPr RCA 1 Rear VGA SVGA Input Hi Density D SUB 15 pin connector 1 Rear DVI Input 1 Re...

Страница 5: ...tically off and enter into Power Saving Mode Press any key on TV or R C or there is signal from PC again TV will be switched on automatically Pixel Movement When this function is on pictures will move on regularly to protect the screen White Screen Display When this function is on the screen will be completely white to clear up slight shadows please see the instruction manual for more details Home...

Страница 6: ...inet Filter Glass Shelve Bar PDP Panel Module Down Cover Module etc Back Cabinet Remarks This drawing is for references only please see the main assembly diagram and wire connecting diagram for details 1 3 2 Circuit Content 6 ...

Страница 7: ...cuit include Power Regulating Circuit RF Circuit VGA Analog Video Digital Video Signal Processing Circuit System Control Circuit Button Control Circuit Reference drawing as below PartⅡ Introduction on Circuit Functions of PT4206 7 ...

Страница 8: ...tion RGB graphics signals from PCs and workstations With a sampling rate capability of up to 140 MHz it can accurately support display resolutions up to 1280x1024 SXGA at 75 Hz The clamped input circuits provide sufficient bandwidth to accurately digitize each pixel The MST9885B provides a high performance highly integrated solution to support the digitization process including the ADCs a voltage ...

Страница 9: ...al SYNC input 30 HSYNC Horizontal SYNC input 43 BAIN Blue analog input 49 SOGIN Sync on Green analog input 48 GAIN Green analog input 54 RAIN Red analog input 29 COAST Hold PLL frequency and do not track HSYNC 38 CLAMP External clamp input we connect it to ground 55 A0 Serial interface address pin 56 SCL I2 C bus clock 57 SDA I2 C bus data 33 FILT PLL connect to external filter 26 27 39 42 45 46 5...

Страница 10: ...46 51 68 80 GND GND 8 NC NC 9 VSUPCAP Supply Voltage Digital Decoupling Circuitry 10 29 36 45 52 V33 Supply Voltage Digital Circuitry 59 69 76 AVCC Analog Voltage 13 SCL I2 C Bus Clock 14 SDA I2 C Bus Data 15 RESQ Reset Input 16 TEST Test Pin 17 VGAV VGAV Input 18 YCOEQ Y C Output Enable Input 19 23 FFIE NC 24 CLK20 Main Clock Output 27 LLC2 Clock Output 28 LLC1 NC 31 34 Y0 Y7 YUV signal output Di...

Страница 11: ...DAT NC 60 CLK5 5 MHz Clock Output 61 NC NC 62 XTAL1 20 25M Analog Crystal Input 63 XTAL2 20 25M Analog Crystal Output 66 VRT Reference Voltage Top Analog 67 I2 CSEL I2 C Bus Address Select 70 VOUT Analog Video Output 71 CIN Chroma Analog Video 5 Input 72 VIN1 Video 1 Analog Input 73 VIN2 Video 2 Analog Input 74 VIN3 Video 3 Analog Input 78 VREF Reference Voltage Top 79 FB1IN Fast Blank Input VPC32...

Страница 12: ...56 YUV0 YUV7 VGPort ITUR656 Pixel Data I O port We use 47 MUTE mute control 48 PW1230E PW1235output enable 49 VGASEL VGA YpbPr select 50 S1 sound system control 51 DVIPD DVI interface standby 54 STANDBY power standby control 56 RST1 peripheral IC reset Graphics Port Pin Descriptions 31 GCLK GPort Pixel Clock input 32 GVS GPort Vertical Sync input 33 GHSSOG GPort Horizontal Sync GPort Sync on Green...

Страница 13: ...al interface select control 203 PORTA4 IR receive signal input 57 58 60 64 PORTB0 PORTB7 Key control input 39 PORTC0 MA EN enable control 40 PORTC1 480ISEL 480I anti copy control 41 PORTC2 RST 1235 PW1235 reset 42 PORTC3 DIGSEL DVI digital interface select 43 PORTC4 LVDSON LVDS enable control 44 PORTC5 S0 sound system control 45 46 PORTC6 PORTC7 LED control 67 RXD Serial Receive Data 68 TXD Serial...

Страница 14: ...PW113 Block Diagram 14 ...

Страница 15: ...deo port blue data input Digital Graphics DG Port Pins 68 DGCLK Digital Graphics DG port pixel clock 67 DGVS Digital Graphics DG port vertical sync 66 DGHS Digital Graphics DG port horizontal sync 91 92 94 95 97 100 DGR0 DGR7 Digital Graphics DG port red data 81 84 86 89 DGG0 DGG7 Digital Graphics DG port green data 70 73 75 76 78 79 DGB0 DGB7 Digital Graphics DG port blue data Analog Display Port...

Страница 16: ... SCL 43 2WA1 Programmable two wire serial bus address bit 1 44 2WA2 Programmable two wire serial bus address bit 2 178 179 181 186 MCUD0 MCUD7 MCU data bus 168 170 172 174 176 177 PORTB1 MCU address bus 190 MCUCS Chip select 191 MCUWR MCUR W signal 192 MCUCMD MCU command signal 188 MCURDY MCU Ready signal Miscellaneous Pin Descriptions 56 TEST Test mode 144 TESTCLK Used for testing can be used to ...

Страница 17: ...y PLL digital power 2 5V 198 DPDVSS Display PLL digital ground 157 AVD33R Analog power 3 3V for R V Pr channel 154 AVD33G Analog power 3 3V for G Y Y channel 151 AVD33B Analog power 3 3V for B U Pb channel 158 AVS33R Analog ground for R V Pr channel 155 AVS33G Analog ground for G Y Y channel 152 AVS33B Analog ground for B U Pb channel 163 ADAVDD Analog power supply 2 5V for the analog display port...

Страница 18: ...18 ...

Страница 19: ...PW1235 Block Diagram 2 2 5 TA2024 general 19 ...

Страница 20: ...ADB A logic low output indicates the input signal has overloaded the amplifier 10 14 OAOUT1 OAOUT2 Input stage output pins 11 15 INV1 INV2 Single ended inputs 12 MUTE Mute control 16 BIASCAP Input stage bias voltage 18 SLEEP Sleep mode control 19 FAULT A logic high output indicates thermal overload 20 35 PGND2 PGND1 Power Grounds high current 22 DGND Digital Ground 24 27 31 28 OUTP2 OUTM2 OUTP1 OU...

Страница 21: ...le of the transmit clock 28 bits of input data are sampled and transmitted At a transmit clock frequency of 65 MHz 24 bits of RGB data and 3 bits of LCD timing and control data FPLINE FPFRAME DRDY are transmitted at a rate of 455 Mbps per LVDS data channel Using a 65 MHz clock the data throughput is 227 Mbytes sec The DS90C383A transmitter can be programmed for Rising edge strobe or Falling edge s...

Страница 22: ...1 12 14 8 10 DGE0 DGE7 8bit green data input 15 19 20 22 23 24 8 16 DBE0 DBE7 8bit blue data input 27 HSYNC Horizontal Sync input 28 VSYNC Vertical Sync input 30 DE pixel display enable 31 TXCLK IN pixel display clock input 32 PWRDWN LVDS control 37 38 41 42 45 46 47 48 TXOUT TXOUT 4 channels LVDS data signal output 39 40 TXCLKOUT TXCLKOUT 1 channel LVDS clock signal output 22 ...

Страница 23: ...DS90CF383 Block Diagram 23 ...

Страница 24: ...tage Differential Signal input data pairs 93 RXC TMDS Low Voltage Differential Signal input clock pair 94 RXC TMDS Low Voltage Differential Signal input clock pair 49 56 QO0 QO7 8bit odd pixel Blue output 59 66 QO8 QO15 8bit even pixel Green output 69 75 77 QO16 QO23 8bit odd pixel Red output 10 17 QE0 QE7 8bit even pixel Blue output 20 27 QE8 QE15 8bit even pixel Green output 30 37 QE16 QE23 8bit...

Страница 25: ...te mode 44 ODCK Output Data Clock This output can be inverted using the OCK_INV pin 46 DE Output Data Enable 47 VSYNC Vertical Sync input control signal 48 HSYNC Horizontal Sync input control signal 18 29 43 57 78 OVCC Output VCC 19 28 45 58 76 OGND Output GND 6 38 67 CVCC Digital Core VCC 5 39 68 GND Digital Core GND 82 84 88 95 DAVCC Analog VCC 99 83 87 89 92 AGND Analog VCC 97 PVCC PLL Analog V...

Страница 26: ...26 ...

Страница 27: ...the same time the Second sound IF signal output The frequency synthesizing and tuning needs two power supplies when work normally 32 V tune voltage and 5 V PLL power supply Moreover 5 and 6 pin of N901 switch the Color system sending out from 44 and 50 pin of PW113 10 pin of N901 outputs video signal follows to Q905 through the video switch circuit switching with the AV S VIDEO Input signal after ...

Страница 28: ...mmunication The 24LC21s of U8 EEPROM saves the hardware concerning display parameter install etc such as the factory model number resolution MST9885 under the control of PW113 bus converts the R G B input 8 bit digital R G B signal 67 pin outputs pixel clock signal DATACK The above signal sends to the PW113 and PW1235s at the same time disposals the format judged by PW113 3 1 1 4 Analog video sign...

Страница 29: ...l data switch with 24bit VGA digital signal disposalled by MST9885 and send to PW113 to transform format for sure the choice is control by PW113 DVI interface 6 7pin is DDC data channel U7 24LC21A is an E2 ROM which stores some DVI data parameter information it connect to DDC data channel by bus at the moment of power on the status information is sent to host to identify after identify according t...

Страница 30: ... 71 Y C PW1235 I channel SV Digital video and clock PW113 SCALER LVDS output DS90C383 D SDRAM BUFF ER PW1235E LVDSON MSP3410G FmorNICAM demodulation SRS WOW sound disposal 67 SIF MUTE 27 28 S1 S0 TA2024 sound amplifier RF controlled by Q3 6 LVDSON control 5 PW1235Econtrol High enable BUFFER and polarity 4 sound switch S0 S1 SO S1 D K 1 0 BG 1 1 I 0 1 M 0 0 Low is power ON 3 MUTE high mute Main con...

Страница 31: ... NTSC NTSC switch by bus 16 uPD64083 comb filter 88 NTSC 制式视频 Sync separate 83 84 73 71 Y C PW1235 I channel SV Digital video and clock PW113 SCALER LVDS output DS90C383 D SDRAM BUFF ER R 54 TA2024 sound amplifier 27 28 MUTE PW1235E LVDSON L 53 SRS WOW sound disposal MSP3410G Sound switch 31 ...

Страница 32: ...switch 17 Y VPC3230 decode PW1235 I channel SV Digital video and clock PW113 SCALER LVDS output DS90C383 D SDRAM BUFF ER MSP3410G Sound switch SRS WOW sound disposal TA2024 sound amplifier 27 28 18 C 72 74 R 54 MUTE PW1235E LVDSON L 53 32 ...

Страница 33: ...hen NTSC switch video s gnal i 16 uPD64083 comb fliter 88 NTSC video Sync separate 83 84 73 71 Y C PW1235 I channel SV Digital video and clock PW113 SCALER disposal LVDS output DS90C383 D SDRAM BUFF ER R 54 TA2024 sound amplifier 27 28 MUTE PW1235E LVDSON L 53 MSP3410G Sound switch SRS WOW sound disposal 33 ...

Страница 34: ...0 switch AD9883 G Pr MSP3410G Sound switch SRS WOW sound disposal 47 MUTE 27 28 L R 48 4 7 9 R G B 43 48 54 Y 2 11 5 Pb TA2024 sound amplifier PW1235E BUFF ER PW113 SCALER LVDSON LVDS output D DS90C383 Format identify PW113 34 ...

Страница 35: ...OW sound disposal 50 TA2024 sound amplifier 27 28 R G PW1235E LVDSON Main control signal 1 RST1 High enable 2 STANBY control Low is power ON 3 MUTE High mute 4 VGASEL control High enable 5 PW1235E control High enable BUFFER and polarity are controlled by Q3 6 LVDSON control MUTE VGASEL 3 6 10 1 13 HS VS U9 PW1235E BUFF ER 31 4 7 9 R G 43 B Not standard mode adjust AD9883 switch the channel R L 51 ...

Страница 36: ...l PW1235 P channel G D G PW1235E BUFF ER BU ER TA2024 sound amplifier 27 28 PW1235E MUTE Not standard mode 非标准模式下 Switch the channel Sound switch SRS WOW sound disposal MSP3410G R 51 L 50 FF SDRAM LVDSON LVDS output D DS90C383 Signal after vertical sync change Digital RGB or YPbPr 36 ...

Страница 37: ...Horizontal and Vertical Sync signal after examined by PW113 displays pc icon on the left and top of PDP panel other part display black If no input after 60 sec it hints to enter save power mode At the moment MST9885 in normal work state examines VGA signal ceaselessly so it can arouse automatically in VGA mode It is said that when VGA signal inputs it can work normally from standby state 3 3 2 whe...

Страница 38: ...ady voltage to Av board 5V etc A12V steady voltage to AV board 8V etc 12VAMP sound amplifier TA2024 power 3 4 2 main power form and power branch 3 4 2 1 5V STpower branch XP801 2 pin 5V ST N803 LM1117 3 3 N804 LM1117 1 8 XP101 11 pin XPK3 11pin K board connect U20 MAX202E U16 PW113 16 37 65 84 137 185pin VLL NK605 remote head VDK1 LED U16 PW113 165 167pin VPP U17 29LV800B 37pin U19 24LC32 8pin U16...

Страница 39: ... pin U27 LM1117 3 3 U26 LM1117 3 3 U1 VPC3230 U6 AD9883A 26 27 39 42 45 46 51 52 59 62 pin VFF U6 AD9883A 34 35 pin VEE VCC U28 LM1086CSX 2 5 U3 PW1235 5 34 93 123 140 175 205 235 pin VXX U3 PW1235 197 199 pin VYY U3 PW1235 58 60 pin VZZ U3 PW1235 149 163 166 pin 2 5 39 ...

Страница 40: ... 243 249 256pin U3 PW1235 51 54 57pin U22 DC90C383 1 9 26pin U10 U12 U14 U15 74LVC16244 7 18 31 42 pin U22 DC90CF383 34pin U22 DC90CF383 44pin U6 AD9883 11 22 23 69 78 79pin U71 74LV32 14pin U1 VPC3230 10 29 36 45 52pin to reduce interference U11 power is divided into VDD VII VJJ by LC filter 97 pin is VII power 82 84 88 95 pin are VJJ power VNN VOO VNN VOO is in order to reduce the interference f...

Страница 41: ...1 12 13pin N901 TDQ 6F7 3 11pin 5VTUNER TV video SIF follow amplifer circuit N702 LM1117 2 5 N703 LM1117 3 3 5V2 N701 input video and output YC filter amplifer circuit 5V 3D U701 uPD64083 53 81 92 93pin A2 5V N701 uPD64083 31 32 45 46 64 100pin D2 5V N701 uPD64083 38pin D3 3V N701 small signal filter amplifer circuit 41 ...

Страница 42: ...3 4 2 5 A12Vpower branch XP805 3pin N651 TA78M08 PC YPbPr sound amplifer 8V N902 TEA6425D 20pin N601 MSP3410G 39pin AVOUT sound amplifer 42 ...

Страница 43: ... pin 5V power supply Check resistance RK2 LBD VDK1 Check K board iack XK01 11 pin 5V power Check power filter and power jack AC 220V input 1 Check XP801 2 pin short circuit to ground whether or not 2 Check mainboard L801 3 Check PW113 reset circuit clock circuit Check mainboard jack XP801 2 pin 5V power Check circuit connect 43 ...

Страница 44: ... 1 check PW113 power impedance 2 checkN803 N804 No check X3 14 318M crystal Yes No change Y2 crystal check PW113 RESET pin voltage Yes check resetcircuit No check AM29LV800BT to PW113 address data control Yes change AM29LV800BT or PW113 and wire between them I2Cbus 1 check VPC3230 PW1235 power circuit 2 check VPC3230 PW1235 reset voltage 3 check VPC3230 PW1235 peripherally circuit normal abnormali...

Страница 45: ...es check mainboard J15 check the line No Yes mend check LVDS signal No 1 LVDS ON is hign or not 2 check PW113 sync pixel clock RGB data sinal No checkDS90c383 power supply Yes check PW113 output port change PW113 No check power supply No check DS90C383 change Yes check PW113 sync pixel clock RGB data sinal Yes check crystal frequent check PW113 change Yes 45 ...

Страница 46: ...and I O sync wave No check VGA jack input abnormality check sync face lifting circuit and peripherally circuit output abnormality no picture only DVI check SiI161B 169 44 48 47 42 pin GCLK GHS GVS GFBK checkSiI161B 169 control signal all abnormality 1 check signal source 2 DVI jack 3 change Sii161B part abnormality other part is following CHECK PW113 G Port 31 35 pin changePW113 No 46 ...

Страница 47: ...PC3230 check and change PW1235 Yes No repair abnormality check AV board connector check TEA6425D I O joint well check TEA6425 power bus change TEA6425 input well but output bad check TEA6425D14 pin video outout check uPD64083 reset clock power changeuPD64083 check uPD64083 I O filter and amplifer circuit Yes check TEA6425D1 pin video signal input checka nd change TEA642 5D No Yes check TDQ 6F7 pow...

Страница 48: ...VGA colour dissimilation only DVI colour dissimilation all colour dissimilation check AD9883A and 74LV16244 R G B digital signal check Sil161B与 and 74LV16244 R G B digital signal change U8 24LC21A check 5 6 pin normal changeu7 24LC21A check 5 6 normal check mainboard panel jack normal DS90C383A normal check PW113 output video siganl normal follow next picture all panel green checkDS90C383A 37 42 4...

Страница 49: ...9883A check PW1235 output data check VPC3230 output check VPC3230 input signal check and change PW1235 No check and change VPC3230 plane crossband interference VGA mode commendatory state change U8 check 5 6 pin DVI mode commendatory state only VGA DVI not commendatory state change U7 check 5 6 pin checkAD9883A and peripherally device check SiI161B and peripherally device 49 ...

Страница 50: ...k MSP3410G output coupling circuitC629 C630 FB5 FB6 C522 C543 Yes check and change TA2024 normal check MSP3410G input signal check 67 pin SISF input TV check sound input other source check MSP3410G power clock reset bus Yes Yes checkTDQ 6F7outp utSIFsignal check SIF filter amplifer circuit normal check and change TDQ 6F7 abnormality check and change MSP3410G normal check signal source sound jack i...

Страница 51: ...Annex 1 装配图 51 ...

Страница 52: ...Annex 2 52 ...

Страница 53: ...电源滤波器组件内联电源线主板组件按键板组件板组件 53 ...

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