PCIe
Slot
Displ
ay on
BMC
CPU
PCIe
Stan
dards
Conn
ector
Widt
h
Bus
Widt
h
Port
No.
Root
Port
(B/D/
F)
Devic
e
(B/D/
F)
Slot
Size
Mezz
1
\
CPU
1
PCIe
3.0
x16
or
two
x8
x16
or
two
x8
Port2
A or
(Port
2A
+Port
2C)
3a:
00.0
3a:
02.0
3b:
00.0
3c:
00.0
-
Mezz
2
\
CPU
1
PCIe
3.0
x16
or
two
x8
x16
or
two
x8
Port3
A or
(Port
3A
+Port
3C)
5d:
00.0
5d:
02.0
5e:
00.0
5f:
00.0
-
Mezz
3
\
CPU
2
PCIe
3.0
x16
or
two
x8
x16
or
two
x8
Port2
A or
(Port
2A
+Port
2C)
ae:
00.0
ae:
02.0
af:
00.0
b0:00.
0
-
Mezz
4
\
CPU
2
PCIe
3.0
x16
or
two
x8
x16
or
two
x8
Port3
A or
(Port
3A
+Port
3C)
d7:00.
0
d7:02.
0
d8:00.
0
d9:00.
0
-
PCIe
SSD 4
disk4
CPU
1
PCIe
3.0
x4
x4
Port
1C
(passi
ng
throu
gh
the
PCIe
Switc
h)
17:02.
0
1e:
00.0
2.5"
drive
PCIe
SSD 5
disk5
CPU
1
PCIe
3.0
x4
x4
Port1
C
(passi
ng
throu
gh
PCIe
Switc
h)
17:02.
0
1f:
00.0
2.5"
drive
Huawei FusionServer Pro CH225 V5 Compute Node
Technical White Paper
5 Hardware Description
Issue 06 (2020-07-31)
Copyright © Huawei Technologies Co., Ltd.
27