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Technical Reference Guide

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4-3

System Support

The PCI bus supports a bus master/target arbitration scheme. A bus master is a device that has
been granted control of the bus for the purpose of initiating a transaction. A target is a device that
is the recipient of a transaction. The Request (REQ), Grant (GNT), and FRAME signals are used
by PCI bus masters for gaining access to the PCI bus. When a PCI device needs access to the PCI
bus (and does not already own it), the PCI device asserts its REQn signal to the PCI bus arbiter (a
function of the system controller component). If the bus is available, the arbiter asserts the GNTn
signal to the requesting device, which then asserts FRAME and conducts the address phase of the
transaction with a target. If the PCI device already owns the bus, a request is not needed and the
device can simply assert FRAME and conduct the transaction. Table 4-2 shows the grant and
request signals assignments for the devices on the PCI bus.

NOTE:
[1] SFF and CMT form factors only.
[2] CMT form factor only

PCI bus arbitration is based on a round-robin scheme that complies with the fairness algorithm
specified by the PCI specification. The bus parking policy allows for the current PCI bus owner
(excepting the PCI/ISA bridge) to maintain ownership of the bus as long as no request is asserted
by another agent. Note that most CPU-to-DRAM accesses can occur concurrently with PCI
traffic, therefore reducing the need for the Host/PCI bridge to compete for PCI bus ownership.

4.2.2 PCI Express Bus Operation

The PCI Express (PCIe) bus is a high-performace extension of the legacy PCI bus specification.
The PCI Express bus uses the following layers:

■

Software/driver layer

■

Transaction protocol layer

■

Link layer

■

Physical layer

Software/Driver Layer

The PCI Express bus maintains software compatibility with PCI 2.3 and earlier versions so that
there is no impact on existing operating systems and drivers. During system intialization, the PCI
Express bus uses the same methods of device discovery and resource allocation that legacy
PCI-based operating systems and drivers are designed to use.

Transaction Protocol Layer

The transaction protocol layer processes read and write requests from the software/driver layer
and generates request packets for the link layer. Each packet includes an identifier allowing any
required responcse packets to be directed to the originator.

Table 4-2.

PCI Bus Mastering Devices

Device

REQ/GNT Line

Note

PCI Connector Slot 1

REQ0/GNT0

[1]

PCI Connector Slot 2

REQ1/GNT1

[1]

PCI Connector Slot 3

REQ2/GNT2

[2]

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Содержание Compaq dc7800 MT

Страница 1: ...61444 001 October 2007 This document provides information on the design architecture function and capabilities of the HP Compaq dc7800 Series Business Desktop Computers This information may be used by engineers technicians administrators or anyone needing detailed information on the products covered ...

Страница 2: ...s Incorporated The only warranties for HP products and services are set forth in the express warranty statements accompanying such products and services Nothing herein should be construed as constituting an additional warranty HP shall not be liable for technical or editorial errors or omissions contained herein This document contains proprietary information that is protected by copyright No part ...

Страница 3: ...1 5 2 Values 1 3 1 5 2 Ranges 1 3 1 6 Common Acronyms and Abbreviations 1 4 2 System Overview 2 1 Introduction 2 1 2 2 Features 2 2 2 3 System Architecture 2 4 2 3 1 Intel Processor Support 2 6 2 3 2 Chipset 2 7 2 3 3 Support Components 2 8 2 3 4 System Memory 2 8 2 3 5 Mass Storage 2 9 2 3 6 Serial and Parallel Interfaces 2 9 2 3 7 Universal Serial Bus Interface 2 9 2 3 8 Network Interface Contro...

Страница 4: ...4 4 Real Time Clock and Configuration Memory 4 9 4 4 1 Clearing CMOS 4 9 4 4 2 Standard CMOS Locations 4 10 4 5 System Management 4 10 4 5 1 Security Functions 4 10 4 5 2 Power Management 4 12 4 5 3 System Status 4 12 4 5 4 Thermal Sensing and Cooling 4 13 4 6 Register Map and Miscellaneous Functions 4 14 4 6 1 System I O Map 4 14 4 6 2 GPIO Functions 4 15 5 Input Output Interfaces 5 1 Introductio...

Страница 5: ...7 5 10 3Power Management Support 5 17 5 10 4 NIC Connector 5 18 5 10 5NIC Specifications 5 18 6 Integrated Graphics Subsystem 6 1 Introduction 6 1 6 2 Functional Description 6 2 6 3 Display Modes 6 4 6 4 Upgrading 6 5 6 5 Monitor Connectors 6 6 6 5 1 Analog Monitor Connector 6 6 6 5 2 Digital Monitor Connector 6 7 7 Power and Signal Distribution 7 1 Introduction 7 1 7 2 Power Distribution 7 1 7 2 ...

Страница 6: ...8 3 1 Boot Device Order 8 3 8 3 2 Network Boot F12 Support 8 3 8 3 3 Memory Detection and Configuration 8 3 8 3 4 Boot Error Codes 8 4 8 4 Client Management Functions 8 5 8 4 1 System ID and ROM Type 8 6 8 4 2 Temperature Status 8 6 8 4 3 Drive Fault Prediction 8 6 8 5 SMBIOS support 8 7 8 6 USB Legacy Support 8 8 8 7 Management Engine Functions 8 8 A Error Messages and Codes Index ...

Страница 7: ...ating and convenient searching through the document A color monitor will also allow the user to view the color shading used to highlight differential data A softcopy of the latest edition of this guide is available for downloading in pdf file format at the following URL www hp com Viewing the file requires a copy of Adobe Acrobat Reader available at no charge from Adobe Systems Inc at the followin...

Страница 8: ...1 2 www hp com Technical Reference Guide Introduction ...

Страница 9: ...s is described as follows WARNING Text set off in this manner indicates that failure to follow directions could result in bodily harm or loss of life CAUTION Text set off in this manner indicates that failure to follow directions could result in damage to equipment or loss of information Text set off in this manner provides information that may be helpful 1 5 2 Values Differences between bytes and...

Страница 10: ...e Interrupt Controller APM advanced power management AOL Alert On LAN ASIC application specific integrated circuit ASF Alert Standard Format AT 1 attention modem commands 2 286 based PC architecture ATA AT attachment IDE protocol ATAPI ATA w packet interface extensions AVI audio video interleaved AVGA Advanced VGA AWG American Wire Gauge specification BAT Basic assurance test BCD binary coded deci...

Страница 11: ...compatibility hole DDC Display Data Channel DDR Double data rate memory DIMM dual inline memory module DIN Deutche IndustriNorm connector type DIP dual inline package DMA direct memory access DMI Desktop management interface dpi dots per inch DRAM dynamic random access memory DRQ data request DVI Digital video interface dword Double word 32 bits EDID extended display identification data EDO extend...

Страница 12: ...d GPIO general purpose I O GPOC general purpose open collector GART Graphics address re mapping table GUI graphic user interface h hexadecimal HW hardware hex hexadecimal Hz Hertz cycles per second ICH I O controller hub IDE integrated drive element IEEE Institute of Electrical and Electronic Engineers IF interrupt flag I F interface IGC integrated graphics controller in inch INT interrupt I O inp...

Страница 13: ...xtensions MPEG Motion Picture Experts Group ms millisecond MSb MSB most significant bit most significant byte mux multiplex MVA motion video acceleration MVW motion video window n variable parameter value NIC network interface card controller NiMH nickel metal hydride NMI non maskable interrupt NRZI Non return to zero inverted ns nanosecond NT nested task flag NTSC National Television Standards Co...

Страница 14: ... pointer RAID Redundant array of inexpensive disks drives RAM random access memory RAS row address strobe rcvr receiver RDRAM Direct Rambus DRAM RGB red green blue monitor input RH Relative humidity RMS root mean square ROM read only memory RPM revolutions per minute RTC real time clock R W Read Write SATA Serial ATA SCSI small computer system interface SDR Singles data rate memory SDRAM Synchrono...

Страница 15: ...IMD extensions STN super twist pneumatic SVGA super VGA SW software TAD telephone answering device TAFI Temperature sensing And Fan control Integrated circuit TCP tape carrier package transmission control protocol TF trap flag TFT thin film transistor TIA Telecommunications Information Administration TPE twisted pair ethernet TPI track per inch TTL transistor transistor logic TV television TX tran...

Страница 16: ...ect current VESA Video Electronic Standards Association VGA video graphics adapter VLSI very large scale integration VRAM Video RAM W watt WOL Wake On LAN WRAM Windows RAM ZF zero flag ZIF zero insertion force socket Table 1 1 Continued Acronyms and Abbreviations Acronym or Abbreviation Description ...

Страница 17: ...sor with the Intel Q35 Express chipset these systems emphasize performance along with industry compatibility These models feature a similar architecture incorporating both PCI 2 3 and PCIe buses All models are easily upgradeable and expandable to keep pace with the needs of the office enterprise Figure 2 1 HP Comapq dc7800 Business PCs This chapter includes the following topics Features 2 2 System...

Страница 18: ...etwork interface controller providing 10 100 1000Base T support Plug n Play compatible with ESCD support Intelligent Manageability support Intel vPro Technology using Active Management Technology AMT 3 0 on select models Security features including Flash ROM Boot Block Diskette drive disable boot disable write protect Power on password Administrator password Serial parallel port disable SFF and CM...

Страница 19: ...2 SDVO card height 4 2 in length 10 5 in 6 Full height PCI slots require installation of PCI riser card field option full height dimensions height 4 2 in length 6 875 in Table 2 1 Feature Difference Matrix by Form Factor USDT SFF CMT Memory type of sockets Maximum memory 2 SODIMM 4GB 4 DIMM 8GB 4 DIMM 8GB Serial ports 0 1 std 1 opt 1 1 std 1 opt 1 Parallel ports 0 1 1 DVI D graphics port 1 0 0 Dri...

Страница 20: ...ugh a 800 1066 1333 MHz Front Side Bus FSB and communicates with the ICH9 DO component through the Direct Media Interface DMI The integrated graphics controller of the Q35 on SFF and CMT systems can be upgraded through a PCI Express PCIe x16 graphics slot All systems include a serial ATA SATA hard drive in the standard configuration The USDT model supports a Slimline Optical Drive through a legacy...

Страница 21: ...SB Ports 5 Serial I F 2 Diskette I F 2 Kybd Mouse I F x16 slot PEG 2 PCIe x1 slots 4 SATA AD1884 Subsystem Optical PCI 2 3 slots 3 Keyboard NIC I F Mouse Diskette 2 Audio I F LPC I F PCI Cntlr DMI DMI Power Supply Notes 3 0 slots in USDT 1 or 2 slots in SFF 3 slots in CMT SATA to PATA Bridge 1 Drive Integrated Audio 4 1 MiniCard slot in USDT 2 slots in SFF 2 slots in CMT Analog Monitor Digital Mon...

Страница 22: ...ions SSE SSE2 and SSE3 for enhancing 3D graphics and speech processing performance The system board includes a zero insertion force ZIF Socket T designed for mounting an LGA775 type processor package CAUTION The USDT form factor can support a processor rated up to 65 watts The SFF and CMT form factors can support a processor rated up to 95 watts Exceeding these limits can result in system damage a...

Страница 23: ...ating system AMT capabilities include System asset recovery hardware and software configuration data OS independent system wellness and healing Software virus protection management Table 2 3 Chipset Components and Functionality Components Function Q35 GMCH Intel Graphics Media Accelerator 3100 integrated graphics controller PCIe x16 graphics interface SFF and CMT only SDRAM controller supporting u...

Страница 24: ...e SFF and CMT form factors provide four DIMM sockets and support a total of eight gigabytes of memory SODIMM and DIMM components are NOT interchangeable Table 2 4 Support Component Functions Component Name Function SCH5327 I O Controller Keyboard and pointing device I F Diskette I F 1 Serial I F COM1and COM2 1 Parallel I F LPT1 LPT2 or LPT3 1 PCI reset generation Interrupt IRQ serializer Power but...

Страница 25: ...p to 115 200 as well as two high speed baud rates of 230K and 460K The parallel interface is Enhanced Parallel Port EPP1 9 and Enhanced Capability Port ECP compatible and supports bi directional data transfers 2 3 7 Universal Serial Bus Interface All models provide ten Universal Serial Bus USB ports Two ports are accessible at the front of the unit six ports are accessible on the rear panel and tw...

Страница 26: ...system These systems use the integrated High Definitions audio controller of the chipset and the ADI AD1884 High Definition audio codec HD audio provides improvements over AC 97 audio such as higher sampling rates refined signal interfaces and audio processors with a higher signal to noise ratio The audio line input jack can be re configured as a microphone input and multi streaming is supported T...

Страница 27: ...actory Configuration Parameter Operating Non operating Ambient Air Temperature 50o to 95o F 10o to 35o C max rate of change 10 C Hr 22o to 140o F 30o to 60o C max rate of change 20 C Hr Shock w o damage 5 Gs 1 20 Gs 1 Vibration 0 000215 G2 Hz 10 300 Hz 0 0005 G2 Hz 10 500 Hz Humidity 10 90 Rh 28o C max wet bulb temperature 5 95 Rh 38 7o C max wet bulb temperature Maximum Altitude 10 000 ft 3048 m ...

Страница 28: ...ns 4 Applicable to unit in desktop orientation only and assumes reasonable type of load such as a monitor Table 2 8 Physical Specifications Parameter USDT 2 SFF 2 CMT 3 Height 2 60 in 6 60 cm 3 95 in 10 03 cm 17 63 in 44 8 cm Width 9 90 in 25 15 cm 13 3 in 33 78 cm 7 0 in 16 8 cm Depth 10 0 in 25 40 cm 14 9 in 37 85 cm 17 8 in 45 21 cm Weight 1 7 0 lb 3 18 kg 18 75 lb 8 50 kg 26 2 lb 1 1 89 kg Loa...

Страница 29: ...edia Type 3 5 in 1 44 MB 720 KB diskette Height 1 3 bay 1 in Bytes per Sector 512 Sectors per Track High Density Low Density 18 9 Tracks per Side High Density Low Density 80 80 Read Write Heads 2 Average Access Time Track to Track high low Average high low Settling Time Latency Average 3 ms 6 ms 94 ms 169 ms 15 ms 100 ms ...

Страница 30: ... 12x 12x DVD RW 8x 8x DVD RW 8x 6x DVD R DL 8x 8x DVD R DL 8x 8x DVD ROM 16x na DVD ROM DL 8x na DVD R 16x 16x DVD R 16x 16x CD ROM 48x na CD RW 32x 32x CD R 48x 48x DVD RAM 12x 12x DVD RW 8x 8x DVD RW 8x 6x DVD R DL 8x 8x DVD R DL 8x 8x DVD ROM 16x na DVD ROM DL 8x na DVD R 16x 16x DVD R 16x 16x CD ROM 48x na CD RW 32x 32x CD R 48x 48x Maximum Transfer Rate Reads DVD 21 6 KB s CD 7 2 KB s DVD 21 ...

Страница 31: ...B 160 GB 250 GB 4 Drive Size 2 5 3 5 in 1 2 5 3 5 in 1 3 5 in Interface SATA SATA SATA Transfer Rate 1 5 3 0 Gb s 2 1 5 3 0 Gb s 2 3 0 Gb s Drive Protection System Support Yes Yes Yes Typical Seek Time w settling Single Track Average Full Stroke 0 8 ms 9 ms 17 ms 0 8 ms 9 ms 17 ms 1 0 ms 1 1 ms 18 ms Disk Format logical blocks 156 301 488 320 173 056 488 397 168 Rotation Speed 5400 7200 10K RPM 3 ...

Страница 32: ...2 16 www hp com Technical Reference Guide System Overview ...

Страница 33: ...d use the Q35 chipset Figure 3 1 These systems support PC2 6400 and PC2 5300 DDR2 memory modules Figure 3 1 Processor Memory Subsystem Architecture This chapter includes the following topics Intel Pentium processor 3 2 Memory subsystem 3 3 Processor Q35 GMCH Cntrl SDRAM XMM1 Channel A DIMM DIMM DIMM DIMM XMM3 XMM4 1 XMM2 1 FSB I F Note 1 Not present on USDT form factor Intel Intel Channel B or SOD...

Страница 34: ...rom the main processing loop Rapid Execution Engine Arithmetic Logic Units ALUs run at twice 2x processing frequency for higher throughput and reduced latency Up to 8 MB of L2 cache Using a 32 byte wide interface at processing speed the large L2 cache provides a substantial increase Advanced dynamic execution Using a larger 4K branch target buffer and improved prediction algorithm branch mis predi...

Страница 35: ...e Reference Guide for processor installation instructions These sysems are available with one of the following processors listed in Table 3 1 NOTE 1 Standard Intel feature set including EM64T XD and EIST support Refer to www Intel com for detailed information CAUTION The USDT form factor can support a processor with a maximum power consumption of 65 watts The SFF and CMT form factors can support a...

Страница 36: ...n and set the system accordingly as follows Single channel mode memory installed for one channel only Dual channel asymetric mode memory installed for both channels but of unequal channel capacities Dual channel interleaved mode recommended memory installed for both channels and offering equal channel capacities proving the highest performance These systems support memory modules with the followin...

Страница 37: ...due to system resource requirements Addressing memory above 4 GB requires a 64 bit operating system 3 3 2 Memory Mapping and Pre allocation Figure 3 2 shows the system memory map The Q35 Express chipset includes a Management Engine that pre allocates a portion of system memory 16 MB for one module 32 MB for two modules for managment functions In addition the internal graphics controller pre alloca...

Страница 38: ...ory area can through the north bridge be mapped to DRAM or to PCI space Graphics RAM area is mapped to PCI locations High BIOS Area DMI APIC PCI Top of DRAM 16 MB 8 GB TSEG IGC 1 64 MB DOS 640 KB 1 FFFF FFFEh 1 MB Main BIOS 00FF FFFFh FFE0 0000h 000F FFFFh Base Memory Extended BIOS Legacy Video Expansion Area 0000 0000h 0010 0000h 0100 0000h Main Area F000 0000h Memory Area Memory Memory Area Comp...

Страница 39: ...to the appropriate PCI specification or the PCI web site www pcisig com These systems implement the following types of PCI buses PCI 2 3 Legacy parallel interface operating at 33 MHz PCI Express High performance interface capable of using multiple TX RX high speed lanes of serial data streams 4 2 1 PCI 2 3 Bus Operation The PCI 2 3 bus consists of a 32 bit path AD31 00 lines that uses a multiplexe...

Страница 40: ...xpr Bridge Integrated Graphics Cntlr 0 0 0 28 1 2 0 0 0 PCI Express x16 graphics slot 0 0 1 82801EB ICH9 PCI Bridge LPC Bridge Serial ATA Controller 1 SMBus Controller Serial ATA Controller 2 Thermal System USB 1 1 Controller 1 USB 1 1 Controller 2 USB 1 1 Controller 3 USB 1 1 Controller 4 USB 1 1 Controller 5 USB 2 0 Controller 1 USB 2 0 Controller 2 Network Interface Controller Intel HD audio co...

Страница 41: ...ing policy allows for the current PCI bus owner excepting the PCI ISA bridge to maintain ownership of the bus as long as no request is asserted by another agent Note that most CPU to DRAM accesses can occur concurrently with PCI traffic therefore reducing the need for the Host PCI bridge to compete for PCI bus ownership 4 2 2 PCI Express Bus Operation The PCI Express PCIe bus is a high performace ...

Страница 42: ...he initialization process two PCI Express devices will negotiate for the number of lanes available and the speed the link can operate at In a x1 single lane interface all data bytes are transferred serially over the lane In a multi lane interface data bytes are distributed across the lanes using a multiplex scheme 4 2 3 Option ROM Mapping During POST the PCI bus is scanned for devices that contain...

Страница 43: ...NTA 27 AD23 3 3 VDC 48 AD10 GND 07 INTB INTC 28 GND AD22 49 GND AD09 08 INTD 5 VDC 29 AD21 AD20 50 Key Key 09 PRSNT1 Reserved 30 AD19 GND 51 Key Key 10 RSVD 5 VDC 31 3 3 VDC AD18 52 AD08 C BE0 1 1 PRSNT2 Reserved 32 AD17 AD16 53 AD07 3 3 VDC 12 GND GND 33 C BE2 3 3 VDC 54 3 3 VDC AD06 13 GND GND 34 GND FRAME 55 AD05 AD04 14 RSVD 3 3 AUX 35 IRDY GND 56 AD03 GND 15 GND RST 36 3 3 VDC TRDY 57 GND AD0...

Страница 44: ...1 10 3 3 Vaux 3 3 VDC 38 PETn5 GND 66 PETp12 GND 1 1 WAKE PERST 39 GND PERp5 67 PETn12 GND 12 RSVD GND 40 GND PERn5 68 GND PERp12 13 GND REFCLK 41 PETp6 GND 69 GND PERn12 14 PETp0 REFCLK 42 PETn6 GND 70 PETp13 GND 15 PETn0 GND 43 GND PERp6 71 PETn13 GND 16 GND PERp0 44 GND PERn6 72 GND PERp13 17 PRSNT2 PERn0 45 PETp7 GND 73 GND PERn13 18 GND GND 46 PETn7 GND 74 PETp14 GND 19 PETp1 RSVD 47 GND PERp...

Страница 45: ...terrupt INTR input to the microprocessor The microprocessor halts execution to determine the source of the interrupt and then services the peripheral as appropriate Most IRQs are routed through the I O controller of the super I O component which provides the serializing function A serialized interrupt stream is then routed to the ICH component Interrupts may be processed in one of two modes select...

Страница 46: ...hod by which a device accesses system memory without involving the microprocessor Although the DMA method has been traditionally used to transfer blocks of data to or from an ISA I O device PCI devices may also use DMA operation as well The DMA method reduces the amount of CPU interactions with memory freeing the CPU for other processing tasks For detailed information regarding DMA operation refer...

Страница 47: ...power supply The battery is located in a battery holder on the system board and has a life expectancy of three or more years When the battery has expired it is replaced with a CR2032 or equivalent 3 VDC lithium battery 4 4 1 Clearing CMOS The contents of configuration memory including the Power On Password can be cleared by the following procedure 1 Turn off the unit 2 Disconnect the AC power cord...

Страница 48: ... operating system and application software Table 4 6 Configuration Memory CMOS Map Location Function Location Function 00 0Dh Real time clock 24h System board ID 0Eh Diagnostic status 25h System architecture data 0Fh System reset code 26h Auxiliary peripheral configuration 10h Diskette drive type 27h Speed control external drive 1 1h Reserved 28h Expanded base mem size IRQ12 12h Hard drive type 29...

Страница 49: ...sword The Setup utility may be configured to be always changeable or changeable only by entering a password Refer to the previous procedure Power On Setup Password for clearing the Setup password Cable Lock Provision These systems include a chassis cutout on the rear panel for the attachment of a cable lock mechanism I O Interface Security The serial parallel USB and diskette interfaces may be dis...

Страница 50: ...and 45 of the SCH5317 I O controller provide the lock and unlock signals to the solenoid A locked hood may be bypassed by removing special screws that hold the locking mechanism in place The special screws are removed with the Smart Cover Lock Failsafe Key 4 5 2 Power Management These systems provide baseline hardware support of ACPI and APM compliant firmware and software Key power consuming comp...

Страница 51: ...ed off Hot processor or power supply will result in starting fan s The RPM speed of all fans is the result of the temperature of the CPU as sensed by speed control circuitry The fans are controlled to run at the slowest quietest speed that will maintain proper cooling Table 4 8 System Operational Status LED Indications System Status PowerLED Beeps 2 Action Required S0 System on normal operation St...

Страница 52: ...d to their corresponding headers to ensure proper cooling of the system 4 6 Register Map and Miscellaneous Functions This section contains the system I O map and information on general purpose functions of the ICH9 and I O controller 4 6 1 System I O Map Table 4 9 lists the fixed addresses of the input output I O ports ...

Страница 53: ...9Fh DMA Controller 00A0 00B1h Interrupt Controller 2 00B2h 00B3h APM Control Status Ports 00B4 00BDh Interrupt Controller 00C0 00DFh DMA Controller 2 00F0h Coprocessor error register 0170 0177h IDE Controller 2 active only if standard I O space is enabled for secondary controller 01F0 01F7h IDE Controller 1 active only if standard I O space is enabled for primary controller 0278 027Fh Parallel Por...

Страница 54: ...GPIO ports Power Hard drive LED control for indicating system events refer to Table 4 8 Hood lock unlock controls the lock bar mechanism Thermal shutdown control turns off the CPU when temperature reaches certain level Processor present speed detection detects if the processor has been removed The occurrence of this event will during the next boot sequence initiate the speed selection routine for ...

Страница 55: ... porting of data and that are controlled through I O mapped registers The following I O interfaces are covered in this chapter SATA interface 5 2 PATA interface 5 3 Diskette drive interface 5 4 Serial interfaces 5 5 Parallel interface 5 6 Keyboard pointing device interface 5 7 Universal serial bus interface 5 8 Audio subsystem 5 9 Network interface controller 5 10 ...

Страница 56: ...stallation Intel Matrix RAID provides exceptional storage performance with increased data protection for configurations using dual drive arrays A software solution is included that provides full management and status reporting of the RAID array and the BIOS ROM also supports RAID creation naming and deletion of RAID arrays The standard 7 pin SATA connector is shown in the figure below Figure 5 1 7...

Страница 57: ...he figure below Figure 5 2 44 pin Slim IDE Connector P21on system board Table 5 2 44 Pin Slim IDE Connector Pinout Pin Signal Pin Signal Pin Signal Pin Signal 1 RESET 2 GND 23 DIOW 24 GND 3 DD7 4 DD8 25 DIOR 26 GND 5 DD6 6 DD9 27 IORDY 28 CSEL 7 DD5 8 DD10 29 DMACK 30 GND 9 DD4 10 DD1 1 31 INTRQ 32 NC 1 1 DD3 12 DD12 33 DA1 34 PDIAG 13 DD2 14 DD13 35 DA0 36 DA2 15 DD1 16 DD14 37 CS0 38 CS1 17 DD0 ...

Страница 58: ...er 3F5h 375h The first byte identifies the command and the remaining bytes define the parameters of the command The Main Status register 3F4h 374h provides data flow control for the diskette drive controller and must be polled between each byte transfer during the Command phase The Execution phase starts as soon as the last byte of the Command phase is received An Execution phase may involve the t...

Страница 59: ... MEDIA ID Media identification 21 GND Ground 5 GND Ground 22 WR DATA Write data 6 DRV 4 SEL Drive 4 select 23 GND Ground 7 GND Ground 24 WR ENABLE Enable for WR DATA 8 INDEX Media index is detected 25 GND Ground 9 GND Ground 26 TRK 00 Heads at track 00 indicator 10 MTR 1 ON Activates drive motor 27 GND Ground 1 1 GND Ground 28 WR PRTK Media write protect status 12 DRV 2 SEL Drive 2 select 29 GND G...

Страница 60: ...he baud rate of the UART is typically set to match the capability of the connected device While most baud rates may be set at runtime baud rates 230400 and 460800 must be set during the configuration phase The serial interface uses a DB 9 connector as shown in the following figure with the pinout listed in Table 5 4 Figure 5 4 DB 9 Serial Interface Connector as viewed from rear of chassis The stan...

Страница 61: ...increased data transfers are possible up to 2 MB s due to a hardware protocol that provides automatic address and strobe generation EPP revisions 1 7 and 1 9 are both supported For the parallel interface to be initialized for EPP mode a negotiation phase is entered to detect whether or not the connected peripheral is compatible with EPP mode If compatible then EPP mode can be used In EPP mode syst...

Страница 62: ...ed or Host Acknowledge 3 EPP mode user defined ECP modes Fault or Peripheral Req 4 EPP mode Reset ECP modes Initialize or Reverse Req Table 5 5 DB 25 Parallel Connector Pinout Pin Signal Function Pin Signal Function 1 STB Strobe Write 1 14 LF Line Feed 2 2 D0 Data 0 15 ERR Error 3 3 D1 Data 1 16 INIT Initialize Paper 4 4 D2 Data 2 17 SLCTIN Select In Address Strobe 1 5 D3 Data 3 18 GND Ground 6 D4...

Страница 63: ... the keyboard for a minimum of 60 us If the keyboard is transmitting data at that time the transmission is allowed to finish When the 8042 is ready to transmit to the keyboard the 8042 pulls the data line low causing the keyboard to respond by pulling the clock line low as well allowing the start bit to be clocked out of the 8042 The data is then transferred serially LSb first to the keyboard Figu...

Страница 64: ...errupt 5 7 3 Keyboard Pointing Device Interface Connector The legacy light model provides separate PS 2 connectors for the keyboard and pointing device Both connectors are identical both physically and electrically Figure 5 7 and Table 5 6 show the connector and pinout of the keyboard pointing device interface connectors Figure 5 7 PS 2 Keyboard or Pointing Device Interface Connector as viewed fro...

Страница 65: ...ansfer rate of 480 Mb s Table 5 7 shows the mapping of the USB ports USB 5 8 1 USB Connector These systems provide type A USB ports as shown in Figure 5 7 Figure 5 8 Universal Serial Bus Connector as viewed from rear of chassis Table 5 7 ICH9 USB Port Mapping ICH9 Controller Signals USB Connector Location USDT SFF Form Factors CMT Form Factor USB 1 1 1 USB 2 0 1 Data 0P 0N System board header P150...

Страница 66: ...ssary The shield chassis ground and power ground should be tied together at the host end but left unconnected at the device end to avoid ground loops Table 5 8 USB Connector Pinout Pin Signal Description Pin Signal Description 1 Vcc 5 VDC 3 USB Data plus 2 USB Data minus 4 GND Ground Table 5 9 USB Cable Length Data Conductor Size Resistance Maximum Length 20 AWG 0 036 Ω 16 4 ft 5 00 m 22 AWG 0 057...

Страница 67: ... inch mini jack that accepts a stereo microphone Line In This input uses a three conductor stereo 1 8 inch mini jack designed for connection of a high impedance audio source such as a tape deck This jack can be re tasked to a Microphone In function Headphones Out This input uses a three conductor stereo 1 8 inch mini jack that is designed for connecting a set of 32 ohm nom stereo headphones Pluggi...

Страница 68: ...g a time division multiplexed TDM protocol The data lines are qualified by the 24 MHz BCLK signal driven by the audio controller Data is transferred in frames synchronized by the 48 KHz SYNC signal which is derived from the clock signal and driven by the audio controller When asserted typically during a power cycle the RESET signal not shown will reset all audio registers to their default values F...

Страница 69: ...In w 20 db gain Line In 283 Vp p 2 83 Vp p Subsystem Impedance Mic In Line In Line Out minimum expected load Headphones Out minimum expected load 20K ohms 20K ohms 10K ohms 32 ohms Signal to Noise Ratio Line out Headphone out Microphone line in 90 db nom 90 db nom 85 db nom Total Harmonic Distortion THD Line out Headphone out Microphone line in 84 db 80 db 78 db Max Subsystem Power Output to 4 ohm...

Страница 70: ...I 1 1 PXE 2 0 WOL ASF 1 0 IPMI AMT 3 0 Cisco Etherchannel support Link and Activity LED indicator drivers The controller features high and low priority queues and provides priority packet processing for networks that can support that feature The controller s micro machine processes transmit and receive frames independently and concurrently Receive runt under sized frames are not passed on as fault...

Страница 71: ... network with an ASF compliant management console 5 10 3 Power Management Support The NIC features Wired for Management WfM support providing system wake up from network events WOL as well as generating system status messages AOL and supports ACPI power management environments The controller receives 3 3 VDC auxiliary power as long as the system is plugged into a live AC receptacle allowing suppor...

Страница 72: ...orprotocol Modes Supported 10BASE T half duplex 10 Mb s 10Base T full duplex 20 Mb s 100BASE TX half duplex 100 Mb s 100Base TX full duplex 200 Mb s 1000BASE T half duplex 1 Gb s 1000BASE TX full duplex 2 Gb s Standards Compliance IEEE 802 1P 802 1Q IEEE 802 2 IEEE 802 3 802 3ab 802 3ad 802 3u 802 3x 802 3z OS Driver Support MS DOS MS Windows 3 1 MS Windows 95 pre OSR2 98 and 2000 Professional XP ...

Страница 73: ...omical 2D and 3D performance The SFF and CMT systems may be upgraded modified by Installing a PCIe x16 graphics card disables the integrated graphics controller Installing a DVI ADD2 into the PCIe x16 slot to supplement the integrated graphics controller or Installing a graphics card in a PCIe x1 slot disables the integrated controller This chapter covers the following subjects Functional descript...

Страница 74: ...ck Figure 6 1 Q35 IGC Block diagram The IGC provides the following features Rapid pixel and texel rendering using four pipelines that allow 2D and 3D operations to overlap speeding up visual effects reducing the amount of memory for texture storage Zone rendering for optimizing 3D drawing eliminating the need for local graphics memory by reducing the bandwidth Dynamic video memory allocation where...

Страница 75: ... during POST System memory that is pre allocated is not seen by the operating system which will report the total amount of memory installed less the amount of pre allocated memory The IGC will use in standard VGA SVGA modes pre allocated memory as a true dedicated frame buffer If the system boots with the OS loading the IGC Extreme Graphics drivers the pre allocated memory will then be re claimed ...

Страница 76: ...sing the IGC 6 3 Display Modes The IGC supports the following standard display modes for 2D video displays The highest resolution available will be determined by the following factors Memory speed and amount Single or dual channel memory Number and type of monitors Table 6 2 IGC Standard 2D Display Modes Resolution Maximum Refresh Rate Analog Monitor Digital Monitor 640 x 480 85 Hz 60 Hz 800 x 600...

Страница 77: ...t one CRT and digital display Dual digital display support may be possible with future cards and drivers The upgrade procedure is as follows 1 Shut down the system through the operating system 2 Unplug the power cord from the rear of the system unit 3 Remove the chassis cover 4 Install the graphics or ADD2 card into the PCI Express x16 graphics slot 5 Replace the chassis cover 6 Reconnect the powe...

Страница 78: ...video monitor Figure 6 2 DB 15 Analog VGA Monitor Connector as viewed from rear of chassis NOTE 1 Fuse automatically resets when excessive load is removed Table 6 3 DB 15 Monitor Connector Pinout Pin Signal Description Pin Signal Description 1 R Red Analog 9 PWR 5 VDC fused 1 2 G Blue Analog 10 GND Ground 3 B Green Analog 1 1 NC Not Connected 4 NC Not Connected 12 SDA DDC Data 5 GND Ground 13 HSyn...

Страница 79: ...ear of chassis Table 6 4 DB 15 Monitor Connector Pinout Pin Signal Pin Signal 1 TMDS Data 2 13 TMDS Data 3 2 TMDS Data 2 14 5 VDC 3 TMDS Data 2 4 shield 15 Ground 4 TMDS Data 4 16 Hot plug detect 5 TMDS Data 4 17 TMDS Data 0 6 DDC Clock 18 TMDS Data 0 7 DDC Data 19 TMDS Data 0 5 Shield 8 not used 20 TMDS Data 5 9 TMDS Data 1 21 TMDS Data 5 10 TMDS Data 1 22 TMDS Clock Shield 1 1 TMDS Data 1 3 Shie...

Страница 80: ...6 8 www hp com Technical Reference Guide Integrated Graphics Subsystem ...

Страница 81: ...ly unit contained within the system chassis The subassemblies are not interchangeable between the three form factors 7 2 1 USDT Power Distribution The USDT form factor uses an external brick supply that connects to the chassis through a three conductor cable Figure 7 1 All voltages required by the processing circuits peripherals and storage devices are produced on the system board from the 19 0 VD...

Страница 82: ...he block diagram for power generation in the SFF Figure 7 2 SFF Power Generation Block Diagram Table 7 2 lists the specifications of the SFF power supply unit Table 7 1 USDT 135 Watt Power Supply Unit Specifications Parameter Input Line Voltage Range 90 265 VAC Line Frequency 47 63 Hz Input Current Maximum load 90 VAC 2 2 A Output Voltage 19 0 VDC Output Current nominal load 3 0 A Output Current m...

Страница 83: ...am Table 7 2 SFF 240 Watt Power Supply Unit Specifications Range Tolerance Min Current Loading 1 Max Current Surge Current 2 Max Ripple Input Line Voltage 90 264 VAC Line Frequency 47 63 Hz Input AC Current 5 0 A 3 3 VDC Output 4 0 1 A 15 0 A 15 0 A 50 mV 5 08 VDC Output 3 3 0 3 A 17 0 A 17 0 A 50 mV 5 08 AUX Output 3 3 0 0 A 3 0 A 3 5 A 50 mV 12 VDC Output 5 0 1 A 7 5 A 9 0 A 120 mV 12 VDC Output...

Страница 84: ...fication compliance 2 Maximum surge duration for 12Vcpu is 1 second with 12 volt tolerance 10 Table 7 3 CMT 365 Watt Power Supply Unit Specifications Range or Tolerance Min Current Loading 1 Max Current Surge Current 2 Max Ripple Input Line Voltage 1 15 230 VAC auto ranging 90 264 VAC Line Frequency 47 63 Hz Input AC Current 6 0 A 3 3 VDC Output 4 0 10 A 24 0 A 24 0 A 50 mV 5 08 VDC Output 3 3 0 3...

Страница 85: ...and CMT systems is Energy Star 3 0 compliant An Energy Star 4 0 80 Plus compliant power supply unit is used for the SFF and CMT form factors in select configurations The standard USDT power supply unit is compliant with the Energy Star 4 0 specification Conn Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin 10 Pin 1 1 Pin 12 P1 3 3 3 3 RTN 5 RTN 5 RTN POK 5 aux 12 12 3 3 P1 1 3 3 12 RTN PS...

Страница 86: ...ive pulse of which the falling edge results in power control logic asserting PS On signal to Power Supply Assembly which then initializes ACPI four second counter is not active On ACPI Disabled Negative pulse of which the falling edge causes power control logic to de assert the PS On signal ACPI four second counter is not active On ACPI Enabled Pressed and Released Under Four Seconds Negative puls...

Страница 87: ...ower failure power supply is overloaded Check storage devices expansion cards and or system board CPU power connector P3 Blinks red 5 times 1 Hz 1 Pre video memory error Incompatible or incorrectly seated DIMM Blinks red 6 times 1 Hz 1 Pre video graphics error On system with integrated graphics check replace system board On system with graphics card check replace graphics card Blinks red 7 times 1...

Страница 88: ...ower strip to control system unit power will disable wake up event functionality The wake up sequence for each event occurs as follows Wake On LAN The network interface controller NIC can be configured for detection of a Magic Packet and wake the system up from sleep mode through the assertion of the PME signal on the PCI bus Refer to Chapter 5 Network Support for more information Modem Ring A rin...

Страница 89: ...nsition To S0 by 2 OS Restart Required G0 S0 D0 System fully on OS and application is running all components Maximum N A No G1 S1 C1 D1 System on CPU is executing and data is held in memory Some peripheral subsystems may be on low power Monitor is blanked Low 2 sec after keyboard or pointing device action No G1 S2 3 C2 D2 Standby or suspend System on CPU not executing cache data lost Memory is hol...

Страница 90: ...MT only J68 Stacked keyboard mouse PS 2 connectors J69 VGA monitor DB 15 connector J78 Stacked audio line in headphone line out 1 8 jacks J103 DC input USDT only P1 Power supply connector SFF CMT only P3 Vccp PWRCPU header P5 Control panel power button power LED header P6 Internal speaker header P8 CPU fan header P9 Chassis fan primary header P10 Diskette drive connector SFF CMT only P20 PATA IDE ...

Страница 91: ... UART2 TX DATA 5 GND 7 5 0V 9 2 UART2 RX DATA 4 UART2 DSR 8 GND 6 UART2 RI 10 3 3V aux UART2 RTS 11 UART2 DCD 13 12 Comm B Detect 12V 15 14 12V Serial Port B Header P52 Hood Lock 1 GND 5 2 Coil Conn 4 12V 6 Hood Unlock Hood Lock Header P124 1 Hood SW Detect 2 GND 3 Hood Sensor Hood Sense Header P125 HD LED 1 HD LED 3 GND5 2 PS LED 4 PS LED 8 GND Pwr Btn 7 GND 11 Therm Diode A 13 12 NC Chassis ID0 ...

Страница 92: ...7 12 www hp com Technical Reference Guide Power and Signal Distribution ...

Страница 93: ...versions Windows NT 4 0 SP6 required for PnP support OS 2 ver 2 1 and OS 2 Warp SCO Unix DMI 2 1 Intel Wired for Management WfM ver 2 2 Alert Standard Format ASF 2 0 ACPI and OnNow SMBIOS 2 4 Intel PXE boot ROM for the integrated LAN controller BIOS Boot Specification 1 01 Enhanced Disk Drive Specification 3 0 El Torito Bootable CD ROM Format Specification 1 0 ATAPI Removeable Media Device BIOS Sp...

Страница 94: ...ount of support necessary to allow booting the system from the diskette drive and re flashing the system BIOS ROM with a CD USB or diskette 8 2 2 Changeable Splash Screen A corrupted splash screen may be restored by reflashing the BIOS image through F10 setup running HPQFlash or running FLASHBIN EXE Depending on the system changing customizing the splash screen may only be available with asistance...

Страница 95: ...s displayed even if no USB storage devices are present The hot IPL option is available through the F9 utility which allows the user to select a hot IPL boot device 8 3 2 Network Boot F12 Support The BIOS supports booting the system to a network server The function is accessed by pressing the F12 key when prompted at the lower right hand corner of the display during POST Booting to a network server...

Страница 96: ... LED Audible speaker Meaning Blinks red 2 times 1 Hz None Processor thermal shut down Check air flow fan operation and CPU heat sink Blinks red 3 times 1 Hz None Processor not installed Install or reseat CPU Blinks red 4 times 1 Hz None Power failure power supply is overloaded Check storage devices expansion cards and or system board CPU power connector P3 Blinks red 5 times 1 Hz 5 beeps Pre video...

Страница 97: ... 3 Calling the client management service to perform the desired function The BIOS32 Service Directory is a 16 byte block that begins on a 16 byte boundary between the physical address range of 0E0000h 0FFFFFh The following subsections provide a brief description of key Client Management functions Table 8 2 Client Management Functions INT15 AX Function Mode E800h Get system ID Real 16 32 bit Prot E...

Страница 98: ... retrieve the status of a system s interior temperature This function allows an application to check whether the temperature situation is at a Normal Caution or Critical condition 8 4 3 Drive Fault Prediction The BIOS directly supports Drive Fault Prediction for IDE ATA type hard drives This feature is provided through two Client Management BIOS calls Function INT 15 AX E817h is used to retrieve a...

Страница 99: ...es listed in the following table System information on these systems is handled exclusively through the SMBIOS Table 8 3 System ID Numbers Type Data 0 BIOS Information 1 System Information 2 Base board information 3 System Enclosure or Chassis 4 Processor Information 7 Cache Information 8 Port Connector Information 9 System Slots 13 BIOS Language Information 15 System Event Log Information 16 Phys...

Страница 100: ...t to PS 2 data The data will be passed to the keyboard controller and processed as in the PS 2 interface Changing the delay and or typematic rate of a USB keyboard though BIOS function INT 16 is not supported 8 7 Management Engine Functions The management engine function of Intel AMT allows a system unit to be managed remotely over a network where or not the system is powered up or not1 The system...

Страница 101: ...er pinouts 7 11 I I O controller 2 8 I O map 4 14 integrated graphics controller IGC 6 2 interrupt handling 8259 mode 4 7 interrupt handling APIC mode 4 7 interrupts hardware 4 7 interrupts PCI 4 7 K keyboard interface 5 9 L LED indications boot error code 8 4 LED indications power button status 7 7 M Management engine 8 8 Memory system 2 8 3 4 memory allocation 3 5 6 3 memory map 3 5 model number...

Страница 102: ... 4 22 Smart hood Cover Sensor 2 2 4 21 SMBIOS 8 17 SPD address map 3 7 specifications physical 2 26 socket processor 2 2 system ID 8 16 T Temperature Status 8 16 U Universal Serial Bus USB interface 5 11 upgrading BIOS 8 2 upgrading graphics 6 5 USB 5 22 V VGA connector 6 6 W Web sites Adobe Systems Inc 1 1 HP 1 1 Intel Corporation 1 1 Standard Microsystems Corporation 1 1 USB user group 1 1 ...

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