HOLT ADK-2130mPCIe Скачать руководство пользователя страница 41

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JTAG

M2 M1 M0
FLASH 0 0 1
JTAG 1 0 1

JTAG
FLASH

CONFIG. BANK

FPGA BOOT FLASH

3x2.5mm

0.47uF close to pins
47 and 4.7 near perimeter.

0.47uF close to pins

done

green FPGA Init OK

GND

FIO3
FSCK

FIO0

FSCK

FnCS
FIO1
FIO2

M0
M1

PROGRAM_B

INIT_B

ADDR0

ADDR14

ADDR12

ADDR13

ADDR2

ADDR7

ADDR11

ADDR5

ADDR10

ADDR8

ADDR4
ADDR3

ADDR6

ADDR15

ADDR1

ADDR9

DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

DATA8

DATA9

DATA10

DATA11

DATA12

DATA13

DATA14

DATA15

FIO0
FIO1
FIO2
FIO3

FnCS

DEV11

nWE

DEV10

nRE

DEV00

nRE

DEV01

nWE

DEV02

nCE0

sys_rst_n

DEV12

nCE1

3V3aux

ADDR[15:0]

DATA[15:0]

DEV0[16:0]

DEV1[16:0]

sys_rst_n

ADCINP

ADCINN

VCCO3V3

VCCAUX_1V8

VCCO3V3

3V3aux

VCCO3V3

VCCINT_1V

VCCAUX_1V8

VCCO3V3

MGTAVCC1V

MGTAVTT1V2

VCCINT_1V

VCCAUX_1V8

VCCO3V3

MGTAVCC1V

MGTAVTT1V2

3V3aux

GND

Title

Size

Document Number

R e v

Date:

Sheet

o f

<Doc>

Holt PCIe-Mini dual MIL-STD 1553

Thursday, January 16, 2020

Title

Size

Document Number

R e v

Date:

Sheet

o f

<Doc>

Holt PCIe-Mini dual MIL-STD 1553

Thursday, January 16, 2020

Title

Size

Document Number

R e v

Date:

Sheet

o f

<Doc>

Holt PCIe-Mini dual MIL-STD 1553

Thursday, January 16, 2020

BANK 0

XC7A12T-2CPG238

U2A

TCK_0

TDI_0

W11

TDO_0

V10

TMS_0

W10

DONE_0

U11

DXP_0

A11

GNDADC_0

C12

VCCADC_0

C13

VREFP_0

B12

VN_0

B13

VCCBATT_0

DXN_0

B11

VREFN_0

A13

VP_0

A12

CCLK_0

C11

M0_0

V13

M1_0

W13

INIT_B_0

W12

M2_0

U13

CFGBVS_0

U12

PROGRAM_B_0

U10

VCCO_0

G12

VCCO_0

V11

R13
4.7K

CON8

1
2
3
4
5
6
7
8

R26 1K

R17
10K

R18
4.7K

C21
.1uF

R27 1K

R14

220

BANK 15

XC7A12T-2CPG238

U2C

IO_L6N_T0_VREF_15

A17

IO_L10P_T1_AD4P_15

A14

IO_L10N_T1_AD4N_15

A15

IO_L11P_T1_SRCC_AD12P_15

B16

IO_L11N_T1_SRCC_AD12N_15

A16

IO_L12P_T1_MRCC_AD5P_15

C15

IO_L12N_T1_MRCC_AD5N_15

B15

IO_L13P_T2_MRCC_15

C16

IO_L13N_T2_MRCC_15

B17

IO_L14P_T2_SRCC_15

B18

IO_L14N_T2_SRCC_15

A18

IO_L19N_T3_A21_VREF_15

C17

VCCO_15

B19

VCCO_15

C14

VCCO_15

C18

VCCO_15

G13

R15
1K

R24
4.7K

C33

0.47uF

R22
4.7K

R23
4.7K

S25FL064LABNFM010 or S25FL064LABNFA010

nCS

SO_IO1

WP_IO2

VSS

SI_IO0

SCK

IO3_RESET

VDD

Pad

D10
LED

FB5

FERRITE BEAD

FB6

FERRITE BEAD

C31

0.47uF

XC7A12T-2CPG238

U2B

IO_0_14

D17

IO_L1P_T0_D00_MOSI_14

D18

IO_L1N_T0_D01_DIN_14

D19

IO_L2P_T0_D02_14

E19

IO_L2N_T0_D03_14

F19

IO_L3P_T0_DQS_PUDC_B_14

E17

IO_L3N_T0_DQS_EMCCLK_14

E18

IO_L4P_T0_D04_14

G18

IO_L4N_T0_D05_14

H18

IO_L5P_T0_D06_14

F17

IO_L5N_T0_D07_14

G17

IO_L6P_T0_FCS_B_14

G19

IO_L6N_T0_D08_VREF_14

H19

IO_L7P_T1_D09_14

H17

IO_L7N_T1_D10_14

J17

IO_L8P_T1_D11_14

J19

IO_L8N_T1_D12_14

K19

IO_L9P_T1_DQS_14

L19

IO_L9N_T1_DQS_D13_14

M19

IO_L10P_T1_D14_14

M17

IO_L10N_T1_D15_14

N18

IO_L11P_T1_SRCC_14

K18

IO_L11N_T1_SRCC_14

L18

IO_L12P_T1_MRCC_14

K17

IO_L12N_T1_MRCC_14

L17

IO_L13P_T2_MRCC_14

N19

IO_L13N_T2_MRCC_14

P19

IO_L14P_T2_SRCC_14

N17

IO_L14N_T2_SRCC_14

P18

IO_L15P_T2_DQS_RDWR_B_14

R19

IO_L15N_T2_DQS_DOUT_CSO_B_14

T19

IO_L16P_T2_CSI_B_14

U19

IO_L16N_T2_A15_D31_14

V19

IO_L17P_T2_A14_D30_14

P17

IO_L17N_T2_A13_D29_14

R17

IO_L18P_T2_A12_D28_14

T17

IO_L18N_T2_A11_D27_14

T18

IO_L19P_T3_A10_D26_14

U17

IO_L19N_T3_A09_D25_VREF_14

U18

IO_L20P_T3_A08_D24_14

W17

IO_L20N_T3_A07_D23_14

W18

IO_L21P_T3_DQS_14

V16

IO_L21N_T3_DQS_A06_D22_14

V17

IO_L22P_T3_A05_D21_14

U15

IO_L22N_T3_A04_D20_14

U16

IO_L23P_T3_A03_D19_14

V14

IO_L23N_T3_A02_D18_14

W14

IO_L24P_T3_A01_D17_14

W15

IO_L24N_T3_A00_D16_14

W16

IO_25_14

U14

VCCO_14

K12

VCCO_14

K13

VCCO_14

L12

VCCO_14

L13

VCCO_14

M12

VCCO_14

M13

VCCO_14

N13

C22
.1uF

R25 1K

CON3

C32

4.7uF

C26

4.7uF

R16
10K

C29

0.47uF

74LVC1G14 - SC70

R19

4.7K

C34

0.47uF

C27

0.47uF

R20

4.7K

C23

.1uF

R12
330

R21

4.7K

C30

0.47uF

D2
LED

C25

47uF

SW1

B3U-1100P

C28

.1uF

C24
47uF

Содержание ADK-2130mPCIe

Страница 1: ...AN 2130mPCIe_New 01 20 ADK 2130mPCIe Technical Manual Jan 16 2020...

Страница 2: ...This page intentionally blank...

Страница 3: ...Holt Integrated Circuits 3 REVISION HISTORY Revision Date Description of Change AN 2130mPCIe Rev New 1 16 20 Initial Release...

Страница 4: ...on to the card Application Development Kit ADK contents and how to run the demonstration software using the Holt bootable Flash Drive Use the instructions in this guide to install the Holt software an...

Страница 5: ...TC3545 1 spare 3 3VMOSFET switch 100MHz MEMS OSC Quad SPI FLASH JTAG 8 pin to FPGA 3 3aux VCCINT 1V MGTAVCC1V VCC1 8V JTAG VCCO 3V3 52 pin PCIe conn Xilinx ARTIX 7 XC7A127 2CPG238I 10 x 10 HI 2130 36...

Страница 6: ...h which present a low to the HI 2130 devices which enables 1553 bus transmissions by default Table 8 is a list of the signals and descriptions on the inter connect ribbon J4 connector For board compon...

Страница 7: ...has not tried any other Linux version as of this date Windows support is planned in the future https ubuntu com download 5 Power up the PC Shortly after powering up the computer the green PCIe Link L...

Страница 8: ...s complete optionally launch eclipse to see it working then exit the program It s possible to create a program short cut from a terminal window where eclipse is installed then drag the link to the des...

Страница 9: ...clipse Project Explorer PE window isn t shown type in Project Explorer into the Quick Access window located on the top right corner of the screen and select it from the list of items shown The three p...

Страница 10: ...ble kernel module pcie_lkm ko This module must be loaded into the Linux OS before executing the Demo project or an error will be produced This module provides support for writing and reading HI 2130 d...

Страница 11: ...t is modified and rebuilt the exiting kernel module must be unloaded before the new one is reloaded sudo sh unload_pcie_load sudo sh load_pcie_load These script commands were embedded in the run scrip...

Страница 12: ...rs asking to select either C C Controller Application or Local C C Application Select Local C C Application c The debugger should present main c in a window with the first line of code highlighted in...

Страница 13: ...Holt Integrated Circuits 13...

Страница 14: ...reparations Before running the Demo connect the ribbon cable between the PCIe card and the Break Out board Carefully insert the small ribbon cable to the Mini PCIe Card J4 connector and the other end...

Страница 15: ...chan 0 HIGH READY asserted Setting nMR chan 1 LOW Setting nMR chan 1 HIGH READY asserted Number of Devices found 2 Initial default RT addresses DEV0 RT1 3 DEV0 RT2 1 DEV1 RT1 3 DEV1 RT1 Optionally use...

Страница 16: ...This is useful to see all the system registers at a glance Using sub commands allow moving up and down in memory space This is more useful to see large areas of memory such as RT control blocks BC me...

Страница 17: ...2626 2727 2828 2929 3030 3131 3232 Dev0 MSG 0003 TIME 00042720us BUS A TYPE0 BC to RT CMD1 1BC0 03 R 30 00 DATA 0101 0202 0303 0404 0505 0606 0707 0808 0909 1010 1111 1212 1313 1414 1515 1616 1717 18...

Страница 18: ...303 0404 0505 0606 0707 0808 0909 1010 1111 1212 1313 1414 1515 1616 1717 1818 1919 2020 2121 2222 2323 2424 2525 2626 2727 2828 2929 3030 3131 3232 STA1 1800 Dev0 MSG 0010 TIME 00047602us BUS B TYPE1...

Страница 19: ...in on bus B into the message sequence while running the BC Async demo command a This will only occur once Dev0 MSG 1694 TIME 00070698us BUS B TYPE0 BC to RT CMD1 0822 01 R 01 02 DATA DEAD BEEF STA1 08...

Страница 20: ...v1 b c k RTMT Demo t Traffic Enabled B C K RTMT Demo a A this will be seen much later inter mixed in the messages below With a 2F card a mixed of messages from Dev0 and Dev1 are displayed Dev0 MSG 028...

Страница 21: ...he default is Demo mode Command f reads and displays the states of the FPGA control signals going to both Dev0 and Dev1 The signals are listed in Table 1 in the next section See the next section for a...

Страница 22: ...o Mode vs User Mode For ease of software demonstration a Demo Mode is selected when location INPUT_CONTROL 0x800D is set low and a User Mode is selected when it is high The power up default is Demo Mo...

Страница 23: ...t High to Enable RT1 RT2ENA FPGA Device Enables RT2 0x800B Read Write Set High to Enable RT2 TXINHA TXINHB J4 Connector Inhibits bus 0x800C Read only Hard wired to J4 INPUT_CONTROL FPGA Set Demo mode...

Страница 24: ...re 3 Board References should be pulled high which will drive M2 high For normal use these connections don t need to be altered by the user only if the user wants to customize the Verilog design and wa...

Страница 25: ...oth devices Unique chip select lines nCE0 and nCE1 are used to select between them Table 3 HI 2130 Common Interface Signals to FPGA HI 2130 FPGA BANK PRIMARY CONNECTOR COMMENTS Address pins A15 A0 14...

Страница 26: ...FPGA RT2MC80 34 RT2MC8 output input to FPGA CH0BCENAB0 BCENA 34 YES Default enabled by pull up resistor Can be set low by the connector or the FPGA can override it CH0BCTRIG BCTRIG 34 YES Normally lo...

Страница 27: ...ES Default enabled by pull up resistor Can be set low by the connector or the FPGA can override it CH1BCTRIG BCTRIG 34 YES Normally low Can be pulsed at connector or the FPGA can override it MTRUN1 34...

Страница 28: ...3V3 supply to meet Xilinx power sequencing recommendations to power the SPI Flash MEMS oscillator and the FPGA bank 14 15 and 34 rails Table 6 Power Supply Power Supply Voltage Schematic Name Functio...

Страница 29: ...y Cycle ICC Amps 3 3V 69 ohm load U7 2130 C Temp Board flat open air U8 2130 C Board flat open air 0 100 1 07 70 56 0 1 100 1 86 82 78 0 1 100 1 86 50 with fan 45 with fan 0 1 100 1 78 81 78 0 1 50 1...

Страница 30: ...hassis GND Mounting screw no other connection 10 CHANNEL 1 BPOS MIL STD 1553 CH1 B 11 CHANNEL 1 BNEG MIL STD 1553 CH1 B 12 Chassis GND Mounting screw no other connection 13 CH0INHBIT0 Channel 0 Transm...

Страница 31: ...e design ACTIVE asserts high during any BC RT or SMT command and serves as a good starting point to check when debugging changes to the software or FPGA design See board references for test point boar...

Страница 32: ...Holt Integrated Circuits 32 Figure 3 Board References...

Страница 33: ...summarized the steps necessary to install the Holt Mini PCIe Eclipse project and import the project into Eclipse to allow building the projects and rerunning them See technical guide AN MPCIeVivado T...

Страница 34: ...X F380J476MMAAXEH3 13 1 Res 100 1 1 20W 0201 SMD R7 P122654CT ND Panasonic ERJ 1GNF1000C 14 1 Res 226K 1 1 20W 0201 SMD R2 P122842CT ND Panasonic ERJ 1GNF2263C 15 1 Res 255K 1 1 20W 0201 SMD R5 P12287...

Страница 35: ...96 43875 1 ND TI TPD4E02B04DQAR 39 1 IC Reg Linear 1V 150mA SOT23 5 U3 497 6871 1 ND ST LD39015M10R 40 1 IC Reg Linear 1 2V 150mA SOT23 5 U4 497 6872 1 ND ST LD39015M12R 41 2 IC Inverter 1CH 1 INP SC7...

Страница 36: ...e FFC 20 Pos 0 5mm 5 Long J2B WM11409 ND Molex 0152660213 4 1 24 Inch Triax Plug Cable CH0 AB None MilesTek CA 2014 48 5 1 Aluminum Block 0 75 x2 5 x0 25 Tie Block None OnlineMetals 1142 6 3 Hex Nut 3...

Страница 37: ...X F380J476MMAAXEH3 13 1 Res 100 1 1 20W 0201 SMD R7 P122654CT ND Panasonic ERJ 1GNF1000C 14 1 Res 226K 1 1 20W 0201 SMD R2 P122842CT ND Panasonic ERJ 1GNF2263C 15 1 Res 255K 1 1 20W 0201 SMD R5 P12287...

Страница 38: ...6 43875 1 ND TI TPD4E02B04DQAR 39 1 IC Reg Linear 1V 150mA SOT23 5 U3 497 6871 1 ND ST LD39015M10R 40 1 IC Reg Linear 1 2V 150mA SOT23 5 U4 497 6872 1 ND ST LD39015M12R 41 2 IC Inverter 1CH 1 INP SC70...

Страница 39: ...FC 20 Pos 0 5mm 5 Long J2B WM11409 ND Molex 0152660213 4 2 24 Inch Triax Plug Cable CH0 AB CH1 AB None MilesTek CA 2014 48 5 1 Aluminum Block 0 75 x2 5 x0 25 Tie Block None OnlineMetals 1142 6 3 Hex N...

Страница 40: ...3 B 1 5 Thursday January 16 2020 Title Size Document Number Rev Date Sheet o f Doc A Holt PCIe Mini dual MIL STD 1553 B 1 5 Thursday January 16 2020 C71 0 22uF C16 1uF C9 10pF C1 10uF REFCLK REFCLK PE...

Страница 41: ...1_MRCC_AD5P_15 C15 IO_L12N_T1_MRCC_AD5N_15 B15 IO_L13P_T2_MRCC_15 C16 IO_L13N_T2_MRCC_15 B17 IO_L14P_T2_SRCC_15 B18 IO_L14N_T2_SRCC_15 A18 IO_L19N_T3_A21_VREF_15 C17 VCCO_15 B19 VCCO_15 C14 VCCO_15 C1...

Страница 42: ...MIL STD 1553 B 3 5 Monday September 30 2019 Title Size Document Number Rev Date Sheet o f Doc A Holt PCIe Mini dual MIL STD 1553 B 3 5 Monday September 30 2019 Title Size Document Number Rev Date Shee...

Страница 43: ...MIL STD 1553 B 4 5 Monday September 30 2019 Title Size Document Number Rev Date Sheet o f Doc A Holt PCIe Mini dual MIL STD 1553 B 4 5 Monday September 30 2019 Title Size Document Number Rev Date Shee...

Страница 44: ...STD 1553 B 5 5 Thursday January 16 2020 2x1 6mm 100MHZ OSC U13 OE 1 OUT 3 VDD 4 GND 2 R34 10K R35 10K R32 10K D4 TPD4E02B04DQAR 1 9 2 3 4 7 8 10 6 5 U10A 74LVC2G14 1 6 C63 0 47uF C67 1uF R41 470 U12B...

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